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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TAS3108DCPR датащи(PDF) 13 Page - Texas Instruments |
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TAS3108DCPR датащи(HTML) 13 Page - Texas Instruments |
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13 / 63 page  www.ti.com 3.8.3 2 Channel Right Justified Timing 23 22 SCLK 32Clks LRCLK LeftChannel 24-BitMode 1 20-BitMode 16-BitMode 15 14 MSB LSB SCLK 32Clks RightChannel 2-ChannelRight-Justified(SonyFormat)StereoInput T0034-03 19 18 1 19 18 1 0 0 0 15 14 15 14 23 22 1 15 14 MSB LSB 19 18 1 19 18 1 0 0 0 15 14 15 14 3.8.4 TDM Modes TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 In 2-channel right-justified timing, LRCLK is HIGH when left channel data is transmitted and LOW when right channel data is transmitted. SCLK is a bit clock running at 64 × f S, which clocks in each bit of the data. The first bit of data appears on the data lines 8 bit-clock periods (for 24-bit data) after LRCLK toggles. In the right-justified mode, the last bit clock before LRCLK transitions always clocks the LSB of data. The data is written MSB first and is valid on the rising edge of the bit clock. The TAS3108/TAS3108IA masks unused leading data-bit positions. Figure 3-4. Right justified 64-fS Format The TDM modes on the TAS3108/TAS3108IA provide left justified and I2S formats. Each word in the TDM data stream adheres to the bit placement shown in Figure 3-5 and Figure 3-6. Two cases are illustrated—an I2S data format and a left-justified data format. Submit Documentation Feedback Physical Characteristics 13 Not Recommended for New Designs |
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