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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TAS3108DCPR датащи(PDF) 31 Page - Texas Instruments |
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TAS3108DCPR датащи(HTML) 31 Page - Texas Instruments |
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31 / 63 page  www.ti.com 6.2.1 Multiple-Byte Write D7 D0 ACK Stop Condition Acknowledge I CDevice Addressand 2 Read/WriteBit Subaddress LastDataByte A6 A5 A1 A0 R/W ACK A7 A5 A1 A0 ACK D7 ACK Start Condition Acknowledge Acknowledge Acknowledge FirstDataByte A4 A3 A6 OtherDataBytes ACK Acknowledge D0 D7 D0 T0036-02 6.2.2 Multiple-Byte Read A6 A0 ACK Acknowledge I CDevice Addressand Read/WriteBit 2 R/W A6 A0 R/W ACK A0 ACK D7 D0 ACK Start Condition Stop Condition Acknowledge Acknowledge Acknowledge LastDataByte ACK FirstDataByte RepeatStart Condition Not Acknowledge I CDevice Addressand Read/WriteBit 2 Subaddress OtherDataBytes A7 A6 A5 D7 D0 ACK Acknowledge D7 D0 T0036-04 6.3 I 2C Master-Mode Device Initialization TAS3108, TAS3108IA AUDIO DIGITAL SIGNAL PROCESSORS SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007 For the standard I2C mode (SCL = 100 kHz), worst-case wait state time for an 8-MHz microprocessor clock is on the order of 2 µs. Nominal wait-state time for the same 8-MHz microprocessor clock is on the order of 1 µs. For the fast I2C mode (SCL = 400 kHz) and the same 8-MHz microprocessor clock, worst-case wait-state time can extend up to 10.5 µs in duration. Nominal wait-state time for this same case lies in a range from 2 µs to 4.6 µs. Increasing the microprocessor clock frequency lowers the wait-state time and for the standard I2C mode, a faster microprocessor clock can totally eliminate the presence of wait states. For example, increasing the microprocessor clock to 16 MHz results in no wait states. For the fast I2C mode, faster microprocessor clocks shorten the wait-state time encountered, but do not totally eliminate wait states. Multiple data bytes are transmitted by the master device to slave as shown in Figure 6-3. After receiving each data byte, the TAS3108/TAS3108IA responds with an acknowledge bit. Figure 6-3. Multiple-Byte Write Transfer Multiple data bytes are transmitted by the TAS3108/TAS3108IA to the master device as shown in Figure 6-4. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte. Figure 6-4. Multiple-Byte Read Transfer I2C master-mode operation is enabled following a reset or power-on reset. Master-mode I2C transactions do not start until the I2C bus is idle. The TAS3108/TAS3108IA uses the master mode to download from EEPROM the memory contents for the microprocessor program memory, microprocessor extended memory, audio DSP core program memory, audio DSP core coefficient memory, and audio DSP core data memory. The TAS3108/TAS3108IA, when operating as an I2C master, can execute a complete download of any internal memory or any section of any internal memory without requiring any wait states. Submit Documentation Feedback Microprocessor Controller 31 Not Recommended for New Designs |
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