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Application Information

9.1 Schematics

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007

Figure 9-1 shows a typical TAS3108/TAS3108IA application. In this application, the following conditions

apply:

• TAS3108/TAS3108IA is in clock-slave mode. The audio (SDIN1, SDIN2, SDIN3, SDIN4) and clock

source (MCLKI) are external.

• MCLKI = 12.288 MHz

• Because MCLKI is sourced externally, the TAS3108/TAS3108IA crystal interface is not used. MCLKI

and XTLI are logically ORed together, meaning that when the MCLKI pin is used, the XTALI pin must

be grounded.

• I2C register 0x00 contains the default settings which means:

–

Audio data word size is 24-bit input and 24-bit output.

–

Serial data format is 2 channel, I2S for input and output.

–

I2C data transfer is approximately 400 kbps for both master and slave I2C interfaces.

–

PLL0 = PLL1 = PLL2 = 0 means that fDSPCLK is 11 × MCLKI = 135.2 MHz and that

fI2CSCL = 375 kHz.

–

Sample frequency (fS) is 48 kHz, which requires that fLRCLK = 48 kHz and fSCLKIN = 3.072 MHz.

• Application code and data are loaded from an external EEPROM using the master I2C interface.

• Application commands come from the system microprocessor to the TAS3108/TAS3108IA using the

slave I2C interface.

Good design practice requires isolation between the digital and analog power as shown. Power-supply

capacitors of 10

µF and 0.1 µF should be placed near the power-supply pins AVDD (AVSS) and DVDD

(DVSS).

The TAS3108/TAS3108IA reset needs external glitch protection. Also, reset going HIGH should be

delayed until TAS3108/TAS3108IA internal power is good (~200

µs). This is provided by the 1-kΩ resistor,

µF capacitor, and diode placed near the RESET pin.

It is recommended that a 4.7-

µF capacitor (fast ceramic type) be placed near pin 28 (VR_DIG). This pin

must not be used to source external components.

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