TAS3108DCPR datasheet(46/63 Pages) TI1

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8.5 Timing Characteristics

8.5.1

Master Clock Signals (TAS3108/TAS3108IA)

XTALI

MCLKO

MCLKI

tw(MCLKI)

tf(MCLKO)

tc(1)

tc(2)

tc(3)

tw(MCLKO)

tr(MCLKO)

td(MI-MO)

T0088-01

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007

The following sections describe the timing characteristics of the TAS3108/TAS3108IA.

over recommended operating conditions (unless otherwise noted)

TEST

PARAMETER

MIN

TYP

MAX

UNIT

CONDITIONS

f(XTALI)

Frequency, XTALI (1/ tc(1))

See (1)

6(2)

20(2)

MHz

tc(1)

Cycle time, XTALI

50(2)

166(2)

f(MCLKI)

Frequency, MCLKI (1/ tc(2))

6(2)

MHz

tw(MCLKI)

Pulse duration, MCLKI high

See (3)

0.4 tc(2)

0.5 tc(2)

0.6 tc(2)

MCLKI jitter

±5(2)

f(MCLKO)

Frequency, MCLKO (1/ tc(3))

6(2)

25(2)

MHz

tr(MCLKO)

Rise time, MCLKO

CL = 30 pF

15(2)

tf(MCLKO)

Fall time, MCLKO

CL = 30 pF

15(2)

tw(MCLKO)

Pulse duration, MCLKO high

See (4)

HMCLKO

XTALI master clock source

MCLKO jitter

MCLKI master clock source

See (5)

Delay time, MCLKI rising MCLKO = MCLKI

See (6)

20(2)

td(MI-MO)

edge to MCLKO rising

MCLKO < MCLKI

See (6) (7)

20(2)

edge

(1)

Duty cycle is 50/50.

(2)

This measurement is specified by design.

(3)

Period of MCLKI = TMCLKI = 1 / fMCLKI

(4)

HMCLKO = 1/(2 × MCLKO). MCLKO has the same duty cycle as MCLKI when MCLKO = MCLKI. When MCLKO = 0.5 MCLKI or 0.25

MCLKI, the duty cycle of MCLKO is typically 50%.

(5)

When MCLKO is derived from MCLKI, MCLKO jitter = MCLKI jitter

(6)

Only applies when MCLKI is selected as master source clock

(7)

Also applies to MCLKO falling edge when MCLKO = MCLKI/2 or MCLKI/4.

Figure 8-1. Master Clock Signal Timing Waveforms

Electrical Specifications

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