TAS3108DCPR datasheet(49/63 Pages) TI1

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8.5.4 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I

2C-Bus Devices

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007

STANDARD MODE

FAST MODE

PARAMETER

TEST CONDITIONS

UNIT

MIN

MAX

MIN

MAX

VIL

LOW-level input voltage

–0.5(1)

0.8

–0.5(1)

0.8

VIH

HIGH-level input voltage

Vhys

Hysteresis of inputs

N/A

0.05 VDD

(1)

LOW-level output voltage (open drain or

VOL1

3-mA sink current

0.4(1)

open collector)

Bus capacitance from 10 pF

7 + 0.1 Cb

tof

Output fall time from VIHmin to VILmax

250(1)

to 400 pF

(2) (1)

Input current, each I/O pin

–10

–10(3)

10(3)

µA

SCL pulse duration of spikes that must

tSP(SCL)

N/A

14(4)(1)

be suppressed by the input filter

SDA pulse duration of spikes that must

tSP(SDA)

N/A

22(4)(1)

be suppressed by the input filter

Capacitance, each I/O pin

10(1)

(1)

This measurement in specified by design.

(2)

Cb = capacitance of one bus line in pF. The output fall time is faster than the standard I

2C specification.

(3)

The I/O pins of fast-mode devices must not obstruct the SDA and SDL lines if VDD is switched off.

(4)

These values are valid at the 135-MHz DSP clock rate. If DSP clock is reduced by one half, the tSP doubles.

NOTE

SDA does not have the standard I

2C specification 300-ns internal hold time. SDA must be

valid by the rising and falling edges of SCL.

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