Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
104
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
10.13.4 Analog Output Buffer Control Register
Analog Output Buffer Control Register (ABF_CR, Address = Bank 1, 62h)
10.14 Analog Modulator
The user has the capability to use the Analog Switch
Cap Type A PSoC Blocks in Columns 0 and 2 as ampli-
tude modulators. The Analog Modulator Control Register
(AMD_CR) allows the user to select the appropriate
modulating signal. When the modulating signal is low,
the polarity follows the setting of the ASign bit set in the
Analog Switch Cap Type A Control 0 Register
(ASAxxCR0). When this signal is high, the normal gain
polarity of the PSoC block is inverted.
Table 80:
Analog Output Buffer Control Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/
Write
W
W
W
W
W
W
--
W
Bit Name
ACol1Mux
ACol2Mux
ABUF1EN
ABUF2EN
ABUF0EN
ABUF3EN
Reserved
PWR
Bit 7
: ACol1Mux
0 = Set column 1 input to column 1 input mux output
1 = Set column 1 input to column 0 input mux output
Bit 6
: ACol2Mux
0 = Set column 2 input to column 2 input mux output
1 = Set column 2 input to column 3 input mux output
Bit 5
: ABUF1EN Enables the analog output buffer for Analog Column 1 (Pin P0[5])
0 = Disable analog output buffer
1 = Enable analog output buffer
Bit 4
: ABUF2EN Enables the analog output buffer for Analog Column 2 (Pin P0[4])
0 = Disable analog output buffer
1 = Enable analog output buffer
Bit 3
: ABUF0EN Enables the analog output buffer for Analog Column 0 (Pin P0[3])
0 = Disable analog output buffer
1 = Enable analog output buffer
Bit 2
: ABUF3EN Enables the analog output buffer for Analog Column 3 (Pin P0[2])
0 = Disable analog output buffer
1 = Enable analog output buffer
Bit [1]
: Reserved Must be left as 0
Bit [0]
: PWR Determines power level of all output buffers
0 = Low output power
1 = High output power
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