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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
102
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
Table 79:
Analog Input Select Register
Analog Input Select Register (AMX_IN, Address = Bank 0, 60h)
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
ACI3 [1]
ACI3 [0]
ACI2 [1]
ACI2 [0]
ACI1 [1]
ACI1 [0]
ACI0 [1]
ACI0 [0]
Bit [7:6]
: ACI3 [1:0]
0 0 = ACM3 P0[0]
0 1 = ACM3 P0[2]
1 0 = ACM3 P0[4]
1 1 = ACM3 P0[6]
Bit [5:4]
: ACI2 [1:0]
0 0 = ACM2 P0[1]
0 1 = ACM2 P0[3]
1 0 = ACM2 P0[5]
1 1 = ACM2 P0[7]
ACol2Mux (ABF_CR, Address = Bank1, 62h)
0 = AC2 = ACM2
1 = AC2 = ACM3
Bit [3:2]
: ACI1 [1:0]
0 0 = ACM1 P0[0]
0 1 = ACM1 P0[2]
1 0 = ACM1 P0[4]
1 1 = ACM1 P0[6]
ACol1Mux (ABF_CR, Address = Bank1, 62h)
0 = AC1 = ACM1
1 = AC1 = ACM0
Bit [1:0]
: ACI0 [1:0]
0 0 = ACM0 P0[1]
0 1 = ACM0 P0[3]
1 0 = ACM0 P0[5]
1 1 = ACM0 P0[7]
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