Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
48
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
9.0
Digital PSoC Blocks
9.1
Introduction
PSoC blocks are user configurable system resources.
On-chip digital PSoC blocks reduce the need for many
MCU part types and external peripheral components.
Digital PSoC blocks can be configured to provide a wide
variety of peripheral functions. PSoC Designer Software
Integrated Development Environment provides auto-
mated configuration of PSoC blocks by simply selecting
the desired functions. PSoC Designer then generates
the proper configuration information and can print a
device data sheet unique to that configuration.
Digital PSoC blocks provide up to eight, 8-bit multipur-
pose timers/counters supporting multiple event timers,
real-time clocks, Pulse Width Modulators (PWM), and
CRCs. In addition to all PSoC block functions, communi-
cation PSoC blocks support full-duplex UARTs and SPI
master or slave functions.
As shown in FigureTitle 12, there are a total of eight 8-bit
digital PSoC blocks in this device family configured as a
linear array. Four of these are the Digital Basic Type A
blocks and four are the Digital Communications Type A
blocks. Each of these digital PSoC blocks can be config-
ured independently, or used in combination.
Each digital PSoC block has a unique Interrupt Vector
and Interrupt Enable bit. Functions can be stopped or
started with a user-accessible Enable bit.
The Timer/Counter/CRC/PRS/Deadband functions are
available on the Digital Basic Type A blocks and also the
Digital Communications Type A blocks. The UART and
SPI communications functions are only available on the
Digital Communications Type A blocks.
There are three configuration registers: the Function
Register (DBA00FN-DCA07FN) to select the block func-
tion and mode, the Input Register (DBA00IN-DCA07IN)
to select data input and clock selection, and the Output
Register (DBA00OU-DCA07OU) to select and enable
function outputs.
The three data registers are designated Data 0
(DBA00DR0-DCA07DR0),
Data
1
(DBA00DR1-
DCA07DR1), and Data 2 (DBA00DR2-DCA07DR2). The
function of these registers and their bit mapping is
dependent on the overall block function selected by the
user.
The one Control Register (DBA00CR0-DCA07CR0) is
designated Control 0. The function of this register and its
bit mapping is dependent on the overall block function
selected by the user.
If the CPU frequency is 24 MHz and a PSoC timer/
counter of 24-bits or longer is operating at 48 MHz, a
write to the block Control Register to enable it (for exam-
ple, a call to Timer_1_Start) may not start the block prop-
erly. In the failure case, the first count will typically be
indeterminate as the upper bytes fail to make the first
count correctly. However, on the first terminal count, the
correct period will be loaded and counted thereafter.
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