Analog PSoC Blocks
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
83
10.9 Analog Switch Cap Type A PSoC Blocks
10.9.1
Introduction
The Analog Switch Cap Type A PSoC blocks are built
around an operational amplifier. There are several ana-
log muxes that are controlled by register-bit settings in
the control registers that determine the signal topology
inside the block. There are also four arrays of unit value
capacitors that are located in the feedback path for the
op-amp, and are switched by two phase clocks, PHI1
and PHI2. These four capacitor arrays are labeled A Cap
Array, B Cap Array, C Cap Array, and F Cap Array. There
is also an analog comparator connected to the output
OUT, which converts analog comparisons into digital sig-
nals.
There are three discrete outputs from this block. These
outputs are:
1.
The analog output bus (ABUS), which is an analog
bus resource that is shared by all of the analog
blocks in the analog column for that block.
2.
The comparator bus (CBUS), which is a digital bus
that is a resource that is shared by all of the analog
blocks in a column for that block.
3.
The output bus (OUT), which is an analog bus
resource that is shared by all of the analog blocks in
a column and connects to one of the analog output
buffers, to send a signal externally to the device.
SC Integrator Block A supports Delta-Sigma, Successive
Approximation and Incremental A/D Conversion, Capaci-
tor DACs, and SC filters. It has three input arrays of bina-
rily-weighted
switched
capacitors,
allowing
user
programmability of the capacitor weights. This provides
summing capability of two (CDAC) scaled inputs, and a
non-switched capacitor input. Since the input of SC
Block A has this additional switched capacitor, it is con-
figured for the input stage of such a switched capacitor
biquad filter. When followed by an SC Block B Integrator,
this combination of blocks can be used to provide a full
Switched Capacitor Biquad.
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