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Clocking
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
39
The following diagram shows the PSoC MCU Clock Tree of signals 48M through SLP:
7.2.1
CPU and Sleep Timer Clock Options
The CPU is clocked off the CPU system-clocking signal,
which can be configured to run at one of eight rates. This
selection is independent from all other clock selection
functions. It is completely safe for the CPU to change its
clock rate without a timing hazard. The CPU clock period
is determined by setting the CPU[2:0] bits in the Oscilla-
tor Control 0 Register (OSC_CR0).
The sleep timer is clocked off the SLP system-clocking
signal. The SLEEP[1] and SLEEP[0] bits in the Oscillator
Control 0 Register (OSC_CR0) allow the user to select
from the four available periods.
Figure 9: PSoC MCU Clock Tree of Signals
Internal
Main
Oscillator
External
Crystal
Oscillator
Internal
Low Speed
Oscillator
48M
24M
÷ n
24V1
24V2
CPU
32K
SLP
48 MHz
24 MHz
IMO_TR[7:0]
OSC_CR0[6]
OSC_CR1[7:4]
OSC_CR1[3:0]
OSC_CR0[2:0]
ECO_TR[7:0]
ILO_TR[7:0]
OSC_CR0[7]
OSC_CR0[4:3]
P1[1]
P1[0]
Vcc
Vcc
÷ 1
÷ 2
÷ 4
÷ 8
÷ 16
÷ 32
÷ 128
÷ 256
PLL Lock Enable
IMO Trim Register
ECO Trim Register
ILO Trim Register
24V1 Clock Div isor
24V2 Clock Div isor
CPU Clock Div isor
Sleep Clock Div isor
32 kHz Select
÷ 732
÷ n
÷ 26
÷ 29
÷ 212
÷ 215
Phase
Lock Loop
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