Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
86
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
10.9.2.3
ACMux
The ACMux, as shown in Analog Switch Cap Type A
Block xx Control 1 Register, controls the input muxing for
both the A and C capacitor branches. The high order bit,
ACMux[2], selects one of two inputs for the C branch.
However, when the bit is high, it also overrides the two
low order bits, forcing the A and C branches to the same
source. The resulting condition is used to construct low
pass biquad filters. See the individual AMux and CMux
diagrams.
10.9.2.4
BMuxSCA/SCB
10.9.3 Registers
10.9.3.1
Analog Switch Cap Type A Block xx
Control 0 Register
FCap controls the size of the switched feedback capaci-
tor in the integrator.
ClockPhase controls the internal clock phasing relative
to the input clock phasing. ClockPhase affects the output
of the analog column bus which is controlled by the
AnalogBus bit in Control 2 Register (ASA10CR2,
ASA12CR2, ASA21CR2, ASA23CR2).
ASign controls the switch phasing of the switches on the
bottom plate of the ACap capacitor. The bottom plate
samples the input or the reference.
The ACap bits set the value of the capacitor in the A
path.
Figure 24: BMuxSCA/SCB Connections
B Input Multiplexer Connections
ASB
20
ACA
00
ACA
01
ACA
02
ACA
03
ASA
10
ASB
11
ASA
12
ASB
13
ASA
21
ASB
22
ASA
23
(1)
(2)
(1)
(1)
(2)
(1)
P2.0
P2.3
ABUS3
TRefGND
(2)
(2)
Table 68:
Analog Switch Cap Type A Block xx Control 0 Register
Bit #
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
Read/
Write
RW
RW
RW
RW
RW
RW
RW
RW
Bit Name
FCap
ClockPhase
ASign
ACap[4]
ACap[3]
ACap[2]
ACap[1]
ACap[0]
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