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Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
30
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
September 5, 2002
Figure 7: General Purpose I/O Pins
GPIO
InterruptEnable
(INT_MSK0:5)
Global Input Line
To CPU Bus
IM0
IM1
IM0
IM1
IM0
IM1
GPIO Read
Global Select
DQ
En
Change
Fall
Rise
Interrupt Mode
IM0
IM1
Output
0
0
Suppress Interrupt
0
1
Falling Edge
10
Rising Edge
1
1
Change from last read
Bonding
Pad
Analog In (Ports 0 and 2 Only)
CPU Bus
GPIO Write
5.6K
Global Select
DM0
DM1
5.6K
V
DD
V
SS
V
DD
V
SS
D
Q
DM0
DM1
Drive Mode
DM0
DM1
Output
0
0
Resistive Pulldown
0
1
Strong Drive
1
0
High Z (off)
1
1
Resistive Pullup
DM1
DM0
Global Out
D
Q
1
From
Other
GPIO
Pins
GPIO Int
DM0
DM1
Analog Out (Port 0 Only)