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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VX6953CB датащи(PDF) 38 Page - STMicroelectronics |
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VX6953CB датащи(HTML) 38 Page - STMicroelectronics |
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38 / 107 page  Register map VX6953CB 38/107 8209023 Rev 5 4.11 Fifo water mark [0x0700 to 0x0701] 4.12 DPHY [0x0810 to 0x0811] 4.13 Binning [0x0900 to 0x0902] and [0x170C to 0x1719] Table 19. Fifo water mark registers [0x0700 to 0x0701] Index Byte Register name Data type Default Type Comment 0x0700 Hi fifo_water_mark_pixels 16UI 00.28 RW The level at which data starts to be transmitted out of the FIFO (default is 40) 0x0701 Lo Table 20. DPHY registers [0x0810 to 0x0811] Index Byte Register name Data type Default Type Comment 0x0810 Hi dphy_channel_mbps_for_ui 16UI 00.00 RW CSI-2 DPHY channel in Mbps (10.4 fixed point). This is used by the DPHY to calculate UI (unit interval) value. It does not control the sensor clock set-up, but should normally correspond to those settings. 0x0811 Lo Table 21. Binning registers [0x0900 to 0x0902] Index Byte Register name Data type Default Type Comment 0x0900 binning_mode 8UI 00 RW Binning mode 0 - Disable 1 - Enable 0x0901 binning_type 8UI 00 RW High-nibble - column binning factor Low-nibble - row binning factor 0x0902 binning_weighting 8UI 00 RW 1 - Averaged 2 - Bayer corrected 0x170C Hi Min_frame_length_lines_bin 16UI 00.28 R Minimum frame length (lines) allowed in binning mode: 40 lines 0x170D Lo 0x170E Hi Max_frame_length_lines_bin 16UI FF.FF R Maximum frame length (lines) allowed in binning mode 0x170F Lo 0x1710 Hi Min_line_length_pck_bin 16UI 0A.BE R Minimum line length (pixel clocks) allowed in binning mode 0x1711 Lo 0x1712 Hi Max_line_length_pck_bin 16UI 03.FF R Maximum possible number of pixel clocks per line in binning mode 0x1713 Lo 0x1714 Hi Min_line_blanking_pck_bin 16UI 00.82 R Minimum line blanking allowed in binning mode: 130 pixel clocks 0x1715 Lo |
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