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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VX6953CB датащи(PDF) 97 Page - STMicroelectronics |
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VX6953CB датащи(HTML) 97 Page - STMicroelectronics |
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97 / 107 page  8209023 Rev 5 97/107 VX6953CB Electrical characteristics 12.7.2 CCP interface - timing characteristics The parameters in Table 54 are measured across a terminated 100 Ω transmission line. CCP2_signalling_mode register is set to 1, data/strobe mode. Figure 48. SubLVDS AC timing Note: For further information on the CCP please refer to the SMIA 1.0 Part 2: CCP2 Specification 30-6-04 document. Table 54. CCP interface - timing characteristics Symbol Parameter Min. Max. Unit Fp Average data frequency - 640 Mbits/s Tp Average data period 1.56 - ns Tjitter(1) 1. TPmax-TPmin. Data period jitter - 200 ps tstable Both data and clock at the stable level 780 - ps Trise Rise time of DATA+/DATA-, CLK+/CLK- 300 400 ps Tfall Fall time of DATA+/DATA-, CLK+/CLK- 300 400 ps Tshew(2) 2. Tshew =Tcmpshew + Tchcshew. Total skew between signals - 225 ps tPWR Power up/down time - 20 μs DATA+/ DATA- CLK+/ CLK- Tcmpshew Tstable Tchcshew TPmin TPmax Tfall Trise 80% 0.9V 20% 80% 0.9V 20% |
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