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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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VX6953CB датащи(PDF) 57 Page - STMicroelectronics |
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VX6953CB датащи(HTML) 57 Page - STMicroelectronics |
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57 / 107 page  8209023 Rev 5 57/107 VX6953CB Video timing Figure 21. VX6953CB clock relationships 1. In order to comply with CSI-2 D-PHY specification, the op_sys_clk_freq_mhz minimum output frequency should be higher than 80 MHz. In order to comply with SMIA 1.0 Part 2: CCP2 Specification v1.0, the maximum op_sys_clk_freq_mhz for CCP2 is 640 MHz. The equations relating the input clock frequency to pixel clock frequencies are: 6.2.2 Spread spectrum clock generator The PLL contains a spread spectrum clock generator (SSCG) block for the purposes of EMI reduction. This feature is off by default and is intended for use if channel blocking becomes an issue on the baseband platform. A primary source of EMI is the high speed CCP serial data link. The modulation period and depth are fully programmable. The spread mode is selectable between center spread (default) or down spread. The SSCG registers can only be reprogrammed with new values when the sensor is in software standby mode. Min. 37 Max. 133 pll_multiplier pre_pll_ clk_div Range 1, 2, 4 Ext. input clock External input clock ext_clk_freq_mhz PLL input clock pll_ip_clk_freq_mhz PLL output clock pll_op_clk_freq_mhz Video timing pixel clock vt_pix_clk_freq_mhz Video timing system clock vt_sys_clk_freq_mhz Range 1, 2, 4 vt_sys_clk _div vt_pix_clk _div Min. 4 Max. 10 Output Timing System clock op_sys_clk_freq_mhz Output Timing Pixel clock op_pix_clk_freq_mhz op_pixel _clk_div op_sys_ clk_div(1) Min. 1 Max. 66 Range 8, 10 Max 27MHz 6MHz Min Min Min Min Min Min Min Max Max Max Max Max Max 800MHz 92MHz 44MHz 176MHz 0.433MHz 92MHz 800MHz 4.33MHz 450MHz 800MHz 6MHz 12MHz vt_pix_clk_freq_mhz ext_clk_freq_mhz pll_multiplier × pre_pll_clk_div vt_sys_clk_div vt_pix_clk_div × × ---------------------------------------------------------------------------------------------------------------------------------- = op_pix_clk_freq_mhz ext_clk_freq_mhz pll_multiplier × pre_pll_clk_div op_sys_clk_div op_pix_clk_div × × --------------------------------------------------------------------------------------------------------------------------------------- = |
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