VX6953CB datasheet(56/107 Pages) STMICROELECTRONICS

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Video timing

VX6953CB

56/107

8209023 Rev 5

Binning repair

Binning can introduce some phases errors from the image perspective as it clusters the

output of each color channel. Gr,R,B and Gb binned pixels are located around the same

intersection point on the output lattice.

To reduce this error, a binning IP is integrated into the imaging data path. The IP moves

each binned color channel by 1/8 of an inter-pixel distance. Therefore the top-left Gr pixel

moves into the top-left corner, the R pixel in the top-right moves in the top-right direction.

This is shown in Figure 20.

Figure 20. Binning repair

6.2

Video timing

This section specifies the timing for the image data that is readout from the pixel array and

the output image data. These are not necessarily the same size.

The application of all of the video timing read/write parameters must be retimed to the start

of the frame boundary to ensure that the parameters are consistent within a frame.

The video stream which is output from the VX6953CB contains both video data and other

auxiliary information. The VX6953CB output coding conforms to the CCP RAW8 and

RAW10 data format (see SMIA 1.0 Part 2:CCP2 Specification) including line checksums.

Reference SMIA 1.0 Specification section 5 for a detailed description of video timing.

6.2.1

PLL block

The VX6953CB contains a phase locked loop (PLL) block, which generates all the

necessary internal clocks from the external clock input. Changes to the PLL settings on the

VX6953CB will only be consumed on the software standby to streaming mode transition.

Figure 21 shows the internal functional blocks, which define the relationship between the

external input clock frequency and the pixel clock frequency.

The majority of the logic within the device is clocked by vt_sys_clk however the CCI block is

clocked by the external input clock.

Image after binning

“Displacement” vectors of

the pixels

Image after phase shifts

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