AM79C970A datasheet(159/219 Pages) AMD

159 / 219 page

P R E L I M I N A R Y

AMD

159

Am79C970A

Read/Write

accessible

only

when either the STOP or the

SPND bit is set. The SWSTYLE

following H_RESET and will be

unaffected by S_RESET or by

setting the STOP bit.

BCR21: Interrupt Control

Bit

Name

Description

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–0 INTCON

Reserved locations. The setting

of this register has no effect on

any PCnet-PCI II controller func-

tion. It is only included for

software compatibility with other

PCnet family devices.

Read/Write accessible always.

INTCON

not

affected

S_RESET or by setting the

STOP bit.

BCR22: PCI Latency Register

Bit

Name

Description

Note that bits 15–0 in this register

are programmable through the

external EEPROM.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–8 MAX_LAT

Maximum Latency. Specifies the

maximum arbitration latency the

PCnet-PCI II controller can sus-

tain without causing problems to

the network activity. The register

value specifies the time in units of

1/4 microseconds. MAX_LAT is

aliased to the PCI configuration

space register MAX_LAT (offset

3Fh). The host should use the

value in this register to determine

the setting of the PCI Latency

Timer register.

Read accessible always. Write

accessible only when either the

STOP or the SPND bit is set.

MAX_LAT is set to the value

of FFh by H_RESET which

corresponds to a maximum la-

tency of 63.75 microseconds.

The actual maximum latency the

PCnet-PCI II controller can han-

dle is 153.6

µs which is also the

value for the bus time-out (see

CSR100). MAX_LAT is not af-

fected by S_RESET or by setting

the STOP bit.

7–0 MIN_GNT

Minimum Grant. Specifies the

minimum length of a burst period

the PCnet-PCI II controller needs

to keep up with the network activ-

ity. The length of the burst period

is calculated assuming a clock

rate of 33 MHz. The register

value specifies the time in units of

1/4 microseconds. MIN_GNT is

aliased to the PCI configuration

space register MIN_GNT (offset

3Eh). The host should use the

value in this register to determine

the setting of the PCI Latency

Timer register.

Read accessible always. Write

accessible only when either the

STOP or the SPND bit is set.

MIN_GNT is set to the value of

06h by H_RESET which corre-

sponds to a minimum grant of 1.5

microseconds. 1.5 microseconds

is the time it takes to PCnet-PCI II

controller to read/write 64 bytes.

(16 DWord transfers in burst

mode with one extra wait state

per data phase inserted by the

target.) Note that the default is

only a typical value. It also does

not take into account any de-

scriptor accesses. MIN_GNT is

not affected by S_RESET or by

setting the STOP bit.

Initialization Block

When SSIZE32 (BCR20, bit 8) is set to ZERO, the soft-

ware structures are defined to be 16 bits wide. The base

address of the initialization block must be aligned to a

DWord boundary, i.e. CSR1, bit 1 and 0 must be cleared

to ZERO. When SSIZE32 is set to ZERO, the initializa-

tion block looks like this:

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