AM79C970A datasheet(158/219 Pages) AMD

158 / 219 page

AMD

P R E L I M I N A R Y

158

Am79C970A

PCnet-PCI II controller utilizes

32-bit software structures for the

initialization block and the trans-

mit and receive descriptor en-

tries. When cleared, this bit

indicates that the PCnet-PCI II

controller utilizes 16-bit software

structures for the initialization

block and the transmit and

receive descriptor entries. In this

mode the PCnet-PCI II controller

is backwards compatible with

the Am79C90 C-LANCE and

Am79C960 PCnet-ISA.

The value of SSIZE32 is deter-

mined by the PCnet-PCI II con-

troller according to the setting of

the Software Style (SWSTYLE,

bits 7–0 of this register).

Read

accessible

always.

SSIZE32 is read only. Write op-

erations

will

ignored.

SSIZE32 will be cleared after

H_RESET (since SWSTYLE de-

faults to ZERO) and is not af-

fected by S_RESET or by setting

the STOP bit.

If SSIZE32 is cleared to ZERO,

then bits IADR[31:24] of CSR2

will be used to generate values

for the upper 8 bits of the 32 bit

address

bus

during

master

accesses

initiated

the

PCnet-PCI II controller. This ac-

tion is required, since the 16-bit

software structures will yield

only 24 bits of address for

PCnet-PCI

controller

bus

master accesses.

If SSIZE32 is set to ONE, then

the software structures that are

common to the PCnet-PCI II

controller and the host system

will supply a full 32 bits for each

address pointer that is needed by

the PCnet-PCI II controller for

performing master accesses.

The value of the SSIZE32 bit has

no effect on the drive of the upper

8 address bits. The upper 8 ad-

dress pins are always driven, re-

gardless of the state of the

SSIZE32 bit.

Note that the setting of the

SSIZE32 bit has no effect on the

width for I/O accesses. I/O

access width is determined by

the

state

the

DWIO

bit

(BCR18, bit 7).

7–0 SWSTYLE

Software

Style

The

value in this register determines

the style of register and memory

resources that shall be used by

the PCnet-PCI II controller. The

Software

Style

selection

will

affect the interpretation of a few

bits within the CSR space, the or-

der of the descriptor entries and

the width of the descriptors and

initialization block entries.

All PCnet-PCI II controller CSR

bits

and

BCR

bits

and

all

descriptor, buffer and initializa-

tion block entries not cited in the

table above are unaffected by the

software style selection.

Table 35. Software Styles

SWSTYLE

Initialization

Descriptor

Altered Bit

[7:0]

Style Name CSRPCNET

SSIZE32

Block Entries

Ring Entries

Interpretations

00h

C-LANCE

16-bit software

All bits in CSR4 are

structures, non-burst

used, TMD1[29] is

PCnet-ISA

or burst access

access only

ADD_FCS

01h

ILACC

32-bit software

CSR4[9:8],CSR4[5:4]

structures, non-burst

and CSR4[1:0] have

or burst access

access only

no function, TMD1[29]

is NO_FCS.

02h

PCnet-PCI

32-bit software

All bits in CSR4 are

structures, non-burst

used, TMD1[29] is

or burst access

access only

ADD_FCS

03h

PCnet-PCI II

32-bit software

All bits in CSR4 are

Controller

structures, non-burst

used, TMD1[29] is

or burst access

ADD_FCS

All Other

Undefined

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