AM79C970A datasheet(162/219 Pages) AMD

162 / 219 page

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P R E L I M I N A R Y

162

Am79C970A

A logical address is passed through the CRC generator,

producing a 32 bit result. The high order 6 bits of the

CRC is used to select one of the 64 bit positions in the

Logical Address Filter. If the selected filter bit is set,

the address is accepted and the frame is placed

into memory.

The Logical Address Filter is used in multicast address-

ing schemes. The acceptance of the incoming frame

based on the filter value indicates that the message may

be intended for the node. It is the node’s responsibility to

determine if the message is actually intended for the

node by comparing the destination address of the stored

message with a list of acceptable logical addresses.

If the Logical Address Filter is loaded with all ZEROs

and promiscuous mode is disabled, all incoming logical

addresses except broadcast will be rejected.

PADR

This 48-bit value represents the unique node address

assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and

used for internal address comparison. PADR[0] is com-

pared with the first bit in the destination address of the

incoming frame. It must be ZERO since only the destina-

tion address of a unicast frames is compared to PADR.

The six hex-digit nomenclature used by the ISO 8802-3

(IEEE/ANSI 802.3) maps to the PCnet-PCI II controller

PADR register as follows: the first byte is compared with

PADR[7:0], with PADR[0] being the least significant bit

of the byte. The second ISO 8802-3 (IEEE/ANSI 802.3)

byte is compared with PADR[15:8], again from the least

significant bit to the most significant bit, and so on. The

sixth byte is compared with PADR[47:40], the least sig-

nificant bit being PADR[40].

MODE

The mode register field of the initialization block is cop-

ied into CSR15 and interpreted according to the descrip-

tion of CSR15.

Receive Descriptors

When SWSTYLE (BCR20, bits 7–0) is set to ZERO,

then the software structures are defined to be 16

bits wide, and receive descriptors, (CRDA = Current

Receive Descriptor Address), are as shown in Table 40.

When SWSTYLE (BCR 20, bits 7–0) is set to ONE or

TWO, then the software structures are defined to be 32

bits wide, and receive descriptors, (CRDA = Current

Receive Descriptor Address), are as shown in Table 41.

When SWSTYLE (BCR 20, bits 7–0) is set to THREE,

then the software structures are defined to be 32 bits

wide, and receive descriptors, (CRDA = Current Re-

ceive Descriptor Address), are as shown in Table 42.

Table 40. Receive Descriptor (SWSTYLE = 0)

Address

7–0

CRDA+00h

RBADR[15:0]

CRDA+02h

OWN

ERR

FRAM

OFLO

CRC

BUFF

STP

ENP

RBADR[23:16]

CRDA+04h

BCNT

CRDA+06h

MCNT

Table 41. Receive Descriptor (SWSTYLE = 1,2)

Address

19–16

15–12

11–0

CRDA+00h

RBADR[31:0]

CRDA+04h

OWN

ERR

FRAM

OFLO

CRC

BUFF

STP

ENP

BPE

PAM

LAFM

BAM

RES

1111

BCNT

CRDA+08h

RCC

RPC

0000

MCNT

CRDA+0Ch

RESERVED

Table 42. Receive Descriptor (SWSTYLE = 3)

Address

19–16

15–12

11–0

CRDA+00h

RCC

RPC

0000

MCNT

CRDA+04h

OWN

ERR

FRAM

OFLO

CRC

BUFF

STP

ENP

BPE

PAM

LAFM

BAM

RES

1111

BCNT

CRDA+08h

RBADR[31:0]

CRDA+0Ch

RESERVED

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