AM79C970A datasheet(163/219 Pages) AMD

163 / 219 page

P R E L I M I N A R Y

AMD

163

Am79C970A

RMD0

Bit

Name

Description

31–0 RBADR

Receive Buffer address. This

field contains the address of the

receive buffer that is associated

with this descriptor.

RMD1

Bit

Name

Description

OWN

This bit indicates whether the

descriptor entry is owned by

the host (OWN = 0) or

the

PCnet-PCI

controller

(OWN = 1). The PCnet-PCI II

controller clears the OWN bit af-

ter filling the buffer that the de-

scriptor points to. The host sets

the OWN bit after emptying the

buffer. Once the PCnet-PCI II

controller or host has relin-

quished ownership of a buffer, it

must not change any field in the

descriptor entry.

ERR

ERR is the OR of FRAM, OFLO,

CRC, BUFF or BPE. ERR is set

by the PCnet-PCI II controller

and cleared by the host.

FRAM

Framing error indicates that the

incoming

frame

contains

non-integer multiple of eight bits

and there was an FCS error. If

there was no FCS error on the in-

coming frame, then FRAM will

not be set even if there was a

non-integer multiple of eight bits

in the frame. FRAM is not valid in

internal loopback mode. FRAM is

valid only when ENP is set and

OFLO is not. FRAM is set by

the PCnet-PCI II controller and

cleared by the host.

OFLO

Overflow error indicates that the

receiver has lost all or part of the

incoming frame, due to an inabil-

ity to move data from the receive

FIFO into a memory buffer before

the internal FIFO overflowed.

OFLO is valid only when ENP

is not set. OFLO is set by

the PCnet-PCI II controller and

cleared by the host.

CRC

CRC indicates that the receiver

has detected a CRC (FCS) error

on the incoming frame. CRC is

valid only when ENP is set and

OFLO is not. CRC is set by

the PCnet-PCI II controller and

cleared by the host.

BUFF

Buffer error is set any time the

PCnet-PCI II controller does not

own the next buffer while data

chaining a received frame. This

can occur in either of two ways:

1. The OWN bit of the next

buffer is ZERO.

2. FIFO overflow occurred be-

fore

the

PCnet-PCI

controller was able to read

the

OWN

bit

the

next descriptor.

If a Buffer Error occurs, an

Overflow Error may also occur in-

ternally in the FIFO, but will not

be reported in the descriptor

status entry unless both BUFF

and OFLO errors occur at the

same time. BUFF is set by the

PCnet-PCI

controller

and

cleared by the host.

STP

Start of Packet indicates that this

is the first buffer used by the

PCnet-PCI II controller for this

frame. If STP and ENP are both

set to ONE, the frame fits into a

single buffer. Otherwise, the

frame is spread over more than

one

buffer.

When

LAPPEN

(CSR3, bit 5) is cleared to ZERO,

STP is set by the PCnet-PCI II

controller and cleared by the

host. When LAPPEN is set to

ONE, STP must be set by

the host.

ENP

End of Packet indicates that

this is the last buffer used by

the PCnet-PCI II controller for

this frame. It is used for data

chaining buffers. If both STP and

ENP are set, the frame fits into

one buffer and there is no data

chaining. ENP is set by the

PCnet-PCI

controller

and

cleared by the host.

BPE

Bus Parity Error is set by the

PCnet-PCI II controller when a

parity error occurred on the bus

interface during a data transfers

to a receive buffer. BPE is valid

only when ENP, OFLO or BUFF

are set. The PCnet-PCI II control-

ler will only set BPE when the ad-

vanced parity error handling is

enabled by setting APERREN

(BCR20, bit 10) to ONE. BPE is

AM79C970A датащи(PDF) 163 Page - Advanced Micro Devices

AM79C970A датащи(HTML) 163 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL