AM79C970A datasheet(160/219 Pages) AMD

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P R E L I M I N A R Y

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Am79C970A

Table 36. Initialization Block (SSIZE32 = 0)

Address

Bits 15–13

Bit 12

Bits 11–8

Bits 7–4

Bits 3–0

IADR+00h

MODE 15–00

IADR+02h

PADR 15–00

IADR+04h

PADR 31–16

IADR+06h

PADR 47–32

IADR+08h

LADRF 15–00

IADR+0Ah

LADRF 31–16

IADR+0Ch

LADRF 47–32

IADR+0Eh

LADRF 63–48

IADR+10h

RDRA 15–00

IADR+12h

RLEN

RES

RDRA 23–16

IADR+14h

TDRA 15–00

IADR+16h

TLEN

RES

TDRA 23–16

Table 37. Initialization Block (SSIZE32 = 1)

Bits

Address

31–28

27–24

23–20

19–16

15–12

11–8

7–4

3–0

IADR+00h

TLEN

RES

RLEN

RES

MODE

IADR+04h

PADR 31–00

IADR+08h

RES

PADR 47–32

IADR+0Ch

LADR 31–00

IADR+10h

LADR 63–32

IADR+14h

RDRA 31–00

IADR+18h

TDRA 31–00

Note that the PCnet-PCI II controller performs DWord

accesses to read the initialization block. This statement

is always true, regardless of the setting of the

SSIZE32 bit.

When SSIZE32 (BCR20, bit 8) is set to ONE, the soft-

ware structures are defined to be 32 bits wide. The base

address of the initialization block must be aligned to a

DWord boundary, i.e. CSR1, bits 1 and 0 must be

cleared to ZERO. When SSIZE32 is set to ONE, the

initialization block looks as shown in Table 37.

RLEN AND TLEN

When SSIZE32 (BCR20, bit 8) is set to ZERO, the soft-

ware structures are defined to be 16 bits wide, and the

RLEN and TLEN fields in the initialization block are each

3 bits wide. The values in these fields determine the

number of transmit and receive Descriptor Ring Entries

(DRE) which are used in the descriptor rings. Their

meaning is as follows:

Table 38. R/TLEN Decoding (SSIZE32 = 0)

R/TLEN

No. of DREs

000

001

010

011

100

101

110

111

128

If a value other than those listed in the above table is de-

sired, CSR76 and CSR78 can be written after initializa-

tion is complete.

When SSIZE32 (BCR20, bit 8) is set to ONE, the soft-

ware structures are defined to be 32 bits wide, and the

RLEN and TLEN fields in the initialization block are each

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