AM79C970A datasheet(156/219 Pages) AMD

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P R E L I M I N A R Y

156

Am79C970A

Table 33. EEDET Setting

EEDET

Value

EEPROM

Result of Automatic EEPROM Read

(BCR19[3])

Connected?

Result if PREAD is Set to ONE

Operation Following H_RESET

EEPROM read operation is attempted.

First TWO EESK clock cycles are

Entire read sequence will occur,

generated, then EEPROM read

checksum failure will result, PVALID

operation is aborted and PVALID

is cleared to ZERO.

Yes

EEPROM read operation is attempted.

First TWO EESK clock cycles are

Entire read sequence will occur,

generated, then EEPROM read

checksum operation will pass, PVALID

operation is aborted and PVALID is

is set to ONE.

cleared to ZERO.

EEPROM read operation is attempted.

Entire read sequence will occur,

checksum failure will result, PVALID

checksum failure will result, PVALID is

is cleared to ZERO.

cleared to ZERO.

Yes

EEPROM read operation is attempted.

Entire read sequence will occur,

checksum operation will pass, PVALID

is set to ONE.

12–5

RES

Reserved locations. Written as

ZEROs, read as undefined.

EEN

EEPROM port enable. When this

bit is set to ONE, it causes the

values of ECS, ESK, and EDI to

be driven onto the EECS, EESK,

and EEDI pins, respectively. If

EEN is cleared to ZERO and no

EEPROM

read

function

currently active, then EECS will

be driven LOW and the EESK

and EEDI pins change their

function to

LED1 and LNKST and

are controlled by BCR5 and

BCR4, respectively.

Read accessible always. Write

accessible only when either the

STOP or the SPND bit is set.

EEN is cleared to ZERO by

H_RESET and is unaffected by

S_RESET or by setting the

STOP bit.

RES

Reserved location. Written as

ZERO and read as undefined.

ECS

EEPROM Chip Select. This bit is

used to control the value of the

EECS pin of the Microwire inter-

face when the EEN bit is set to

ONE and the PREAD bit is

cleared to ZERO. If EEN is set to

ONE and PREAD is cleared to

ZERO and ECS is set to ONE,

then the EECS pin will be forced

to a HIGH level at the rising edge

of the next clock following bit pro-

gramming. If EEN is set to ONE

and PREAD is cleared to ZERO

and ECS is cleared to ZERO,

then the EECS pin will be forced

to a LOW level at the rising edge

of the next clock following bit pro-

gramming. ECS has no effect on

the output value of the EECS pin

unless the PREAD bit is cleared

to ZERO and the EEN bit is set

to ONE.

Read accessible always. Write

accessible only when either the

STOP or the SPND bit is set.

ECS is cleared to ZERO by

H_RESET and is not affected by

S_RESET or by setting the

STOP bit.

ESK

EEPROM Serial Clock. This bit

and the EDI/EDO bit are used to

control

host

access

the

EEPROM. Values programmed

to this bit are placed on to the

EESK pin at the rising edge of the

next clock following bit program-

ming, except when the PREAD

bit is set to ONE or the EEN bit is

cleared to ZERO. If both the ESK

bit and the EDI/EDO bit values

are changed during one BCR19

write operation while EEN is set

to ONE, then setup and hold

times of the EEDI pin value with

respect to the EESK signal edge

are not guaranteed.

ESK has no effect on the EESK

pin unless the PREAD bit is

cleared to ZERO and the EEN bit

is set to ONE.

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