AM79C970A datasheet(157/219 Pages) AMD

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Am79C970A

Table 34. Microwire Interface Pin Assignment

PREAD or

Auto Read in

RST Pin

Progress

EEN

EECS

EESK

EEDI

High

Low

Tri-State

Low

Active

Low

BCR19[2]

BCR19[1]

BCR19[0]

Low

LED1

LNKST

Read accessible always. Write

accessible only when either the

STOP or the SPND bit is set.

ESK is set to ONE by H_RESET

and is not affected by S_RESET

or by setting the STOP bit.

EDI/EDO

EEPROM

Data

In/EEPROM

Data Out. Data that is written to

this bit will appear on the EEDI

output of the Microwire interface,

except when the PREAD bit is set

to ONE or the EEN bit is cleared

to ZERO. Data that is read from

this bit reflects the value of

the

EEDO

input

the

Microwire interface.

EDI/EDO has no effect on the

EEDI pin unless the PREAD bit is

cleared to ZERO and the EEN bit

is set to ONE.

Read accessible always. Write

accessible only when either the

STOP or the SPND bit is set.

EDI/EDO is cleared to ZERO by

H_RESET and is not affected by

S_RESET or by setting the

STOP bit.

BCR20: Software Style

Bit

Name

Description

This register is an alias of the lo-

cation CSR58. Accesses to/from

this register are equivalent to ac-

cesses to CSR58.

31–16

RES

Reserved locations. Written as

ZEROs and read as undefined.

15–11

RES

Reserved locations. Written as

ZEROs and read as undefined.

APERREN

Advanced Parity Error Handling

Enable. When APERREN is set

to ONE, the BPE bits (RMD1 and

TMD1, bit 23) are used to indi-

cated

parity

error

data

transfers to the receive and

transmit buffers. Note that since

the

advanced

parity

error

handling uses an additional bit in

the descriptor, SWSTYLE (bits

7–0 of this register) must be set

to ONE, TWO or THREE to pro-

gram the PCnet-PCI II controller

to use 32-bitsoftware structures.

APERREN does not affect the re-

porting of address parity errors or

data parity errors that occur

when the PCnet-PCI II controller

is the target of the transfer.

Read accessible always, write

accessible only when either the

STOP or the SPND bit is set.

APERREN

cleared

H_RESET and is not affected by

S_RESET or by setting the

STOP bit.

CSRPCNET

CSR PCnet-ISA configuration.

When set, this bit indicates that

the PCnet-PCI II controller regis-

ter bits of CSR4 and CSR3 will

map directly to the CSR4 and

CSR3 bits of the PCnet-ISA

(Am79C960)

device.

When

cleared, this bit indicates that

PCnet-PCI II controller register

bits of CSR4 and CSR3 will map

directly

the

CSR4

and

CSR3

bits

the

ILACC

(Am79C900) device.

The value of CSRPCNET is

determined by the PCnet-PCI II

controller

according

the

setting of the Software Style

(SWSTYLE,

bits

7–0

this register).

Read

accessible

always.

CSRPCNET is read only. Write

operations

will

ignored.

CSRPCNET will be set after

H_RESET (since SWSTYLE de-

faults to ZERO) and is not

affected by S_RESET or by set-

ting the STOP bit.

SSIZE32

32-Bit Software Size. When set,

this

bit

indicates

that

the

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