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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C970A датащи(PDF) 36 Page - Advanced Micro Devices |
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AM79C970A датащи(HTML) 36 Page - Advanced Micro Devices |
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36 / 219 page  AMD P R E L I M I N A R Y 36 Am79C970A read operation by setting the PREAD bit (BCR19, bit 14). While the EEPROM read is on-going, the PCnet-PCI II controller will disconnect any slave access where it is the target by asserting STOP together with DEVSEL, while driving TRDY high. STOP will stay as- serted until the host removes FRAME. Note that I/O and memory slave accesses will only be disconnected if they are enabled by setting the IOEN or MEMEN bit in the PCI Command register. Without the enable bit set, the cycles will not be claimed at all. Since H_RESET clears the IOEN and MEMEN bits, for the automatic EEPROM read after H_RESET the discon- nect only applies to configuration cycles. A second situation where the PCnet-PCI II controller will generate a PCI disconnect/retry cycle is when the host tries to access any of the I/O resources right after having read the Reset register. Since the access generates an internal reset pulse of about 1 µs in length, all further slave accesses will be deferred until the internal reset operation is completed. 19436A-9 FRAME CLK AD IRDY TRDY C/ BE DEVSEL STOP 1 2345 CMD PAR PAR PAR BE DATA ADDR Figure 6. Disconnect Of Slave Cycle When Busy |
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