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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C970A датащи(PDF) 161 Page - Advanced Micro Devices |
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AM79C970A датащи(HTML) 161 Page - Advanced Micro Devices |
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161 / 219 page  P R E L I M I N A R Y AMD 161 Am79C970A 4 bits wide. The values in these fields determine the number of transmit and receive Descriptor Ring Entries (DRE) which are used in the descriptor rings. Their meaning is as follows: Table 39. R/TLEN Decoding (SSIZE32 = 1) R/TLEN No. of DREs 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 11XX 512 1X1X 512 If a value other than those listed in the above table is de- sired, CSR76 and CSR78 can be written after initializa- tion is complete. RDRA and TDRA TDRA and RDRA indicate where the transmit and re- ceive descriptor rings begin. Each DRE must be located at a16-byte address boundary when SSIZE32 is set to ONE (BCR20, bit 8). Each DRE must be located at an 8-byte address boundary when SSIZE32 is set to ZERO (BCR20, bit 8). LADRF The Logical Address Filter (LADRF) is a 64-bit mask that is used to accept incoming Logical Addresses. If the first bit in the incoming address (as transmitted on the wire) is a ONE, it indicates a logical address. If the first bit is a ZERO, it is a physical address and is compared against the physical address that was loaded through the initialization block. 4 1 CRC GEN SEL 31 26 MUX 63 0 64 MATCH = 1 Packet Accepted MATCH = 0 Packet Rejected MATCH Logical Address Filter (LADRF) 0 6 32-Bit Resultant CRC 1 0 Received Message Destination Address 19436A-48 Figure 2. Address Match Logic |
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