AM79C960KCW datasheet(74/127 Pages) AMD

74 / 127 page

P R E L I M I N A R Y

AMD

1-416

Am79C960

15-5

RES

Reserved locations. Written as

zero and read as undefined.

GPSIEN

This mode places the PCnet-ISA

controller in the GPSI Mode. This

mode will reconfigure the Exter-

nal Address Pins so that the

GPSI port is exposed. This al-

lows bypassing the MENDEC-

TMAU logic. This bit should only

be set if the external logic sup-

ports GPSI operation. Damage

to the device may occur in a non-

GPSI configuration. Refer to the

GPSI section.

RPA

Runt Packet Accept. This bit

forces the CORE receive logic to

accept Runt Packets. This bit al-

lows for faster testing.

2-0

RES

For test purposes only. Reserved

locations. Written as zero and

read as undefined.

ISA Bus Configuration Registers

The ISA Bus Data Port (IDP) allows access to registers

which are associated with the ISA bus. These registers

are called ISA Bus Configuration Registers (ISACSRs),

and are indexed by the value in the Register Address

Port (RAP). The table below defines the ISACSRs which

can be accessed. All registers are 16 bits. The “Default”

value is the value in the register after reset and is

hexadecimal.

ISACSR

MNEMONIC

Default

Name

MSRDA

0005H

Master Mode

Read Active

MSWRA

0005H

Master Mode

Write Active

0002H

Miscellaneous

Configuration

Reserved

N/A

Reserved for

future AMD use

LED0

0000H

Link Integrity

LED1

0084H

Default: RCV

LED2

0008H

Default: RCVPOL

LED3

0090H

Default: XMT

ISACSR0: Master Mode Read Active

Bit

Name

Description

15-4

RES

Reserved locations. Written as

zero and read as undefined.

3-0

MSRDA

This register is used to tune the

MEMR command signal active

time. The value stored in MSRDA

defines the number of 50 ns peri-

ods that the command signal is

active. The default value of 5h in-

dicates 250 ns pulse widths. A

value of 0 or 1 will generate 50 ns

wide commands.

ISACSR1: Master Mode Write Active

Bit

Name

Description

15-4

RES

Reserved locations. Written as

zero and read as undefined.

3-0

MSWRA

This register is used to tune the

MEMW command signal active

time.

The

value

stored

MSWRA defines the number of

50 ns periods that the command

signal is active. The default value

of 5h indicates 250 ns pulse

widths. A value of 0 or 1 will gen-

erate 50 ns wide commands.

ISACSR2: Miscellaneous Configuration

Bit

Name

Description

15 MODE_STATUS Mode Status. This is a read-only

the PCnet-ISA is configured in

shared memory mode.

A set

condition

indicates

shared-

memory while a clear condition

indicates bus-master condition.

14-8

RES

Reserved locations. Written and

read as zero.

EISA_LVL

EISA_LVL allows for EISA level-

sensitive

interrupt

support.

EISA_LVL

cleared

when

RESET

asserted.

When

EISA_LVL is a zero, the IRQ pin

is configured for ISA edge sensi-

tive full CMOS driver. When

EISA_LVL is set by writing a one,

the IRQ pin is configured as an

EISA

level-sensitive

interrupt

open

drain

output.

When

EISA_LVL is set to one, the IRQ

pin assertion level is active low.

6-5

RES

Reserved locations. Written and

read as zero.

ISAINACT

ISAINACT allows for reduced in-

active

timing

appropriate

for

modern

ISA

machines.

ISAINACT

cleared

when

RESET

asserted.

When

ISAINACT is a zero, tMMR3 and

tMMW3 parameters are nomi-

nally 200 ns, which is com-

patible with EISA system. When

ISAINACT is set by writing a one,

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