AM79C960KCW datasheet(66/127 Pages) AMD

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P R E L I M I N A R Y

AMD

1-408

Am79C960

In loopback mode, this bit deter-

mines if the transmitter appends

FCS or if the receiver checks the

FCS.

This bit was called DTCR in the

LANCE (Am7990).

Read/write accessible only when

STOP bit is set.

LOOP

Loopback

Enable

allows

PCnet-ISA controller to operate

in full duplex mode for test pur-

poses.

When

LOOP

“1”,

loopback is enabled. In combina-

tion with INTL and MENDECL,

various loopback modes are de-

fined as follows:

LOOP

INTL

MENDECL

Loopback Mode

Non-loopback

External Loopback

Internal Loopback Include

MENDEC

Internal Loopback Exclude

MENDEC

Read/write accessible only when

STOP bit is set. LOOP is cleared

by RESET.

DTX

Disable Transmit. If this bit is set,

the PCnet-ISA controller will not

access the Transmit Descriptor

Ring and, therefore, no transmis-

sions will occur. DTX = “0” will set

TXON bit (CSR0.4) after STRT

(CSR0.1) is asserted. DTX is de-

fined after the initialization block

is read.

Read/write accessible only when

STOP bit is set.

DRX

Disable Receiver. If this bit is set,

the PCnet-ISA controller will not

access the Receive Descriptor

Ring and, therefore, all receive

frame data are ignored. DRX =

“0” will set RXON bit (CSR0.5) af-

ter STRT (CSR0.1) is asserted.

DRX is defined after the initializa-

tion block is read.

Read/write accessible only when

STOP bit is set.

CSR16: Initialization Block Address Lower

Bit

Name

Description

15-0

IADR

Lower 16 bits of the address of

the Initialization Block. Bit loca-

tion 0 must be zero. This register

is an alias of CSR1. Whenever

this register is written, CSR1 is

updated with CSR16’s contents.

Read/Write

accessible

only

when the STOP bit in CSR0 is

set. Unaffected by RESET.

CSR17: Initialization Block Address Upper

Bit

Name

Description

15-8

RES

Reserved locations. Written as

zero and read as undefined.

7-0

IADR

Upper 8 bits of the address of the

Initialization Block. Bit locations

15-8 must be written with zeros.

This register is an alias of CSR2.

Whenever this register is written,

CSR2 is updated with CSR17’s

contents.

Read/Write

accessible

only

when the STOP bit in CSR0 is

set. Unaffected by RESET.

CSR18-19: Current Receive Buffer Address

Bit

Name

Description

31-24

RES

Reserved locations. Written as

zero and read as undefined.

23-0

CRBA

Contains the current receive

buffer address to which the

PCnet-ISA controller will store in-

coming frame data.

Read/write accessible only when

STOP bit is set.

CSR20-21: Current Transmit Buffer Address

Bit

Name

Description

31-24

RES

Reserved locations. Written as

zero and read as undefined.

23-0

CXBA

Contains the current transmit

buffer address from which the

PCnet-ISA controller is transmit-

ting.

Read/write accessible only when

STOP bit is set.

CSR22-23: Next Receive Buffer Address

Bit

Name

Description

31-24

RES

Reserved locations. Written as

zero and read as undefined.

23-0

NRBA

Contains the next receive buffer

address to which the PCnet-ISA

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