AM79C960KCW datasheet(37/127 Pages) AMD

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P R E L I M I N A R Y

AMD

1-379

Am79C960

scriptor. In any case, lookahead will be performed to the

third buffer and the information gathered will be stored in

the chip, regardless of the state of the ownership bit. As

in the transmit flow, lookahead operations are per-

formed only once.

This activity continues until the PCnet-ISA controller

recognizes the completion of the packet (the last byte of

this receive message has been removed from the

FIFO). The PCnet-ISA controller will subsequently

update the current RDTE status with the end of packet

(ENP) indication set, write the message byte count

(MCNT) of the complete packet into RMD2 and over-

write the “current” entries in the CSRs with the

“next” entries.

Media Access Control

The Media Access Control engine incorporates the es-

sential protocol requirements for operation of a

compliant Ethernet/802.3 node, and provides the inter-

face between the FIFO sub-system and the Manchester

Encoder/Decoder (MENDEC).

The MAC engine is fully compliant to Section 4 of ISO/

IEC 8802-3 (ANSI/IEEE Standard 1990 Second Edition)

and ANSI/IEEE 802.3 (1985).

The MAC engine provides programmable enhanced

features designed to minimize host supervision and pre

or post-message processing. These features include

the ability to disable retries after a collision, dynamic

FCS generation on a packet-by-packet basis, and auto-

matic pad field insertion and deletion to enforce

minimum frame size attributes.

The two primary attributes of the MAC engine are:

s Transmit and receive message data encapsulation

— Framing (frame boundary delimitation, frame

synchronization)

— Addressing (source and destination address

handling)

— Error detection (physical medium transmission

errors)

s Media access management

— Medium allocation (collision avoidance)

— Contention resolution (collision handling)

Transmit And Receive Message Data

Encapsulation

The MAC engine provides minimum frame size enforce-

ment

for

transmit

and

receive

packets.

When

APAD_XMT = 1 (bit 11 in CSR4), transmit messages

will be padded with sufficient bytes (containing 00h) to

ensure that the receiving station will observe an infor-

mation field (destination address, source address,

length/type, data and FCS) of 64 bytes.

When

ASTRP_RCV = 1 (bit 10 in CSR4), the receiver will auto-

matically strip pad bytes from the received message by

observing the value in the length field, and stripping ex-

cess bytes if this value is below the minimum data size

(46 bytes). Both features can be independently over-

ridden to allow illegally short (less than 64 bytes of

packet data) messages to be transmitted and/

or received.

Framing (Frame Boundary Delimitation, Frame

Synchronization)

The MAC engine will autonomously handle the con-

struction of the transmit frame. Once the Transmit FIFO

has been filled to the predetermined threshold (set by

XMTSP in CSR80), and providing access to the channel

is currently permitted, the MAC engine will commence

the 7-byte preamble sequence (10101010b, where first

bit transmitted is a 1). The MAC engine will subse-

quently append the Start Frame Delimiter (SFD) byte

(10101011b) followed by the serialized data from the

Transmit FIFO. Once the data has been completed, the

MAC engine will append the FCS (most significant bit

first) which was computed on the entire data portion of

the message.

Note that the user is responsible for the correct ordering

and content in each of the fields in the frame, including

the destination address, source address, length/type

and packet data.

The receive section of the MAC engine will detect an in-

coming preamble sequence and lock to the encoded

clock. The internal MENDEC will decode the serial bit

stream and present this to the MAC engine. The MAC

will discard the first 8 bits of information before search-

ing for the SFD sequence. Once the SFD is detected, all

subsequent bits are treated as part of the frame. The

MAC engine will inspect the length field to ensure mini-

mum frame size, strip unnecessary pad characters (if

enabled), and pass the remaining bytes through the Re-

ceive FIFO to the host. If pad stripping is performed, the

MAC engine will also strip the received FCS bytes, al-

though the normal FCS computation and checking will

occur. Note that apart from pad stripping, the frame will

be passed unmodified to the host. If the length field has

a value of 46 or greater, the MAC engine will not attempt

to validate the length against the number of bytes con-

tained in the message.

If the frame terminates or suffers a collision before

64 bytes of information (after SFD) have been received,

the MAC engine will automatically delete the frame from

the Receive FIFO, without host intervention.

Addressing (Source and Destination Address

Handling)

The first 6 bytes of information after SFD will be inter-

preted as the destination address field. The MAC engine

provides facilities for physical, logical, and broadcast

address reception. In addition, multiple physical ad-

dresses can be constructed (perfect address filtering)

using external logic in conjunction with the EADI

™

interface.

Error Detection (Physical Medium Transmission

Errors)

The MAC engine provides several facilities which report

and recover from errors on the medium. In addition, the

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