AM79C960KCW datasheet(54/127 Pages) AMD

54 / 127 page

P R E L I M I N A R Y

AMD

1-396

Am79C960

The address and

SROE go active within 20 ns of the

clock going HIGH. Data is required to be valid 5 ns be-

fore the end of the second clock cycle. Address and

SROE have a 0 ns hold time after the end of the second

clock cycle. Note that the PCnet-ISA controller does not

provide a separate SRAM

CS signal; SRAM CS must

always be asserted.

SRAM Private Bus write cycles require three 50 ns clock

periods to guarantee non-negative address setup and

hold times with regard to

SRWE. The timing is illustrated

as follows:

XTAL1

(20 MHz)

Address/

Data

SRWE

16907B-11

XTAL

(20 MHz)

Address/

Data

SRWE

Static RAM Write Cycle

Address and data are valid 20 ns after the rising edge of

the first clock period.

SRWE goes active 20 ns after the

falling edge of the first clock period.

SRWE goes inactive

20 ns after the falling edge of the third clock period.

Address and data remain valid until the end of the third

clock period. Rise and fall times are nominally 5 ns.

Non-negative setup and hold times for address and data

with respect to

SRWE are guaranteed. SRWE has a

pulse width of typically 100 ns, minimum 75 ns.

Transmit Operation

The transmit operation and features of the PCnet-ISA

controller are controlled by programmable options.

Transmit Function Programming

Automatic transmit features, such as retry on collision,

FCS generation/transmission, and pad field insertion,

can all be programmed to provide flexibility in the

(re-)transmission of messages.

Disable retry on collision (DRTY) is controlled by the

DRTY bit of the Mode register (CSR15) in the initializa-

tion block.

Automatic pad field insertion is controlled by the

APAD_XMT bit in CSR4. If APAD_XMT is set, auto-

matic pad field insertion is enabled, the DXMTFCS

feature is over-ridden, and the 4-byte FCS will be added

to the transmitted frame unconditionally. If APAD_XMT

is cleared, no pad field insertion will take place and runt

packet transmission is possible.

The disable FCS generation/transmission feature can

be programmed dynamically on a frame by frame basis.

See the ADD_FCS description of TMD1.

Transmit FIFO Watermark (XMTFW in CSR80) sets the

point at which the BMU (Buffer Management Unit) re-

quests more data from the transmit buffers for the FIFO.

This point is based upon how many 16-bit bus transfers

(2 bytes) could be performed to the existing empty

space in the transmit FIFO.

Transmit Start Point (XMTSP in CSR80) sets the point

when the transmitter actually tries to go out on the me-

dia. This point is based upon the number of bytes written

to the transmit FIFO for the current frame.

When the entire frame is in the FIFO, attempts at trans-

mission of preamble will commence regardless of the

value in XMTSP. The default value of XMTSP is 10b,

meaning 64 bytes full.

Automatic Pad Generation

Transmit frames can be automatically padded to extend

them to 64 data bytes (excluding preamble). This allows

the minimum frame size of 64 bytes (512 bits) for

802.3/Ethernet to be guaranteed with no software inter-

vention from the host/controlling process. Setting the

APAD_XMT bit in CSR4 enables the automatic padding

feature. The pad is placed between the LLC data field

and FCS field in the 802.3 frame. FCS is always added if

the frame is padded, regardless of the state of

DXMTFCS. The transmit frame will be padded by bytes

with the value of 00h. The default value of APAD_XMT is

0, and this will disable auto pad generation after RESET.

16907B-12

Preamble

1010....1010

SYNC

10101011

Dest

ADDR

Srce

ADDR

Length

LLC

Data

Pad

FCS

Bits

Bytes

46-1500

Bytes

ISO 8802–3 (IEEE/ANSI 802.3) Data Frame

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