AM79C960KCW datasheet(70/127 Pages) AMD

70 / 127 page

P R E L I M I N A R Y

AMD

1-412

Am79C960

CSR68-69: Transmit Status Temporary Storage

Bit

Name

Description

31-0

XSTMP

Transmit Status Temporary Stor-

age location.

Read/write accessible only when

STOP bit is set.

CSR70-71: Temporary Storage

Bit

Name

Description

31-0

TMP8

Temporary Storage location.

Read/write accessible only when

STOP bit is set.

CSR72: Receive Ring Counter

Bit

Name

Description

15-0

RCVRC

Receive Ring Counter location.

Contains a Two’s complement

binary number used to number

the current receive descriptor.

This counter interprets the value

in CSR76 as pointing to the first

descriptor; a two’s complement

value of -1 (FFFFh) corresponds

to the last descriptor in the ring.

Read/write accessible only when

STOP bit is set.

CSR74: Transmit Ring Counter

Bit

Name

Description

15-0

XMTRC

Transmit Ring Counter location.

Contains a Two’s complement

binary number used to number

the current transmit descriptor.

This counter interprets the value

in CSR78 as pointing to the first

descriptor; a two’s complement

value of -1 (FFFFh) corresponds

to the last descriptor in the ring.

Read/write accessible only when

STOP bit is set.

CSR76: Receive Ring Length

Bit

Name

Description

15-0

RCVRL

Receive Ring Length. Contains a

Two’s complement binary num-

ber of the receive descriptor ring

length. This register is initialized

during the PCnet-ISA controller

initialization routine based on the

value in the RLEN field of the

initialization block. This register

can be manually altered; the ac-

tual receive ring length is defined

by the current value in this

Read/write accessible only when

STOP bit is set.

CSR78: Transmit Ring Length

Bit

Name

Description

15-0

XMTRL

Transmit Ring Length. Contains

the two’s complement of the

transmit descriptor ring length.

This register is initialized during

the PCnet-ISA controller

initialization routine based on the

value in the TLEN field of the ini-

tialization block. This register can

be manually altered; the actual

transmit ring length is defined by

the current value in this register.

Read/write accessible only when

STOP bit is set.

CSR80: Burst and FIFO Threshold Control

Bit

Name

Description

15-14

RES

Reserved locations. Read as

ones. Written as zero.

13-12RCVFW[1:0]

Receive

FIFO

Watermark.

RCVFW controls the point at

which ISA bus receive DMA is re-

quested in relation to the number

of received bytes in the receive

FIFO.

RCVFW

specifies

the

number of bytes which must be

present (once the frame has

been verified as a non-runt) be-

fore receive DMA is requested.

Note however that in order for re-

ceive DMA to be performed for a

new frame, at least 64 bytes must

have been received. This effec-

tively avoids having to react to

receive frames which are runts or

suffer a collision during the slot

time (512 bit times). If the Runt

Packet Accept feature is en-

abled, receive DMA will be

requested as soon as either the

RCVFW threshold is reached, or

a complete valid receive frame is

detected (regardless of length).

RCVFW is set to a value of 10b

(64 bytes) after RESET.

Read/write accessible only when

STOP bit is set.

AM79C960KCW датащи(PDF) 70 Page - Advanced Micro Devices

AM79C960KCW датащи(HTML) 70 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL