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AM79C960KCW датащи(PDF) 58 Page - Advanced Micro Devices |
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AM79C960KCW датащи(HTML) 58 Page - Advanced Micro Devices |
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58 / 127 page ![]() P R E L I M I N A R Y AMD 1-400 Am79C960 Each status signal is ANDed with its corresponding enable signal. The enabled status signals run to a com- mon OR gate: COL COL E JAB JAB E LNK LNK E RCV RCV E RVPOL RVPOL E XMT XMT E 16907B-14 LED Control Logic The output from the OR gate is run through a pulse stretcher, which consists of a 3-bit shift register clocked at 38 Hz. The data input of the shift register is at logic 0. The OR gate output asynchronously sets all three bits of the shift register when its output goes active. The output of the shift register controls the associated LEDx pin. Thus, the pulse stretcher provides an LED output of 52 ms to 78 ms. |
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