AM79C960KCW datasheet(60/127 Pages) AMD

60 / 127 page

P R E L I M I N A R Y

AMD

1-402

Am79C960

MERR assertion will set the ERR

bit.

MERR is set by the Bus Interface

Unit and cleared by writing a “1”.

Writing a “0” has no effect. MERR

is cleared by RESET or by setting

the STOP bit.

RINT

Receive Interrupt is set after re-

ception of a receive frame and

toggling of the OWN bit in the last

buffer in the Receive Descriptor

Ring.

When RINT is set, IRQ is as-

serted if IENA = 1 and the mask

bit RINTM (CSR3.10) is clear.

RINT is set by the Buffer Man-

agement Unit after the last

receive buffer has been updated

and cleared by writing a “1”. Writ-

ing a “0” has no effect. RINT is

cleared by RESET or by setting

the STOP bit.

TINT

Transmit Interrupt is set after

transmission of a transmit frame

and toggling of the OWN bit in the

last buffer in the Transmit De-

scriptor Ring.

When TINT is set, IRQ is as-

serted if IENA = 1 and the mask

bit TINTM (CSR3.9) is clear.

TINT is set by the Buffer Man-

agement Unit after the last

transmit buffer has been updated

and cleared by writing a “1”.

Writing a “0” has no effect. TINT

is cleared by RESET or by setting

the STOP bit.

IDON

Initialization Done indicates that

the initialization sequence has

completed. When IDON is set,

PCnet-ISA controller has read

the

Initialization

block

from

memory.

When IDON is set, IRQ is as-

serted if IENA = 1 and the mask

bit IDONM (CSR3.8) is clear.

IDON is set by the Buffer Man-

agement

Unit

after

the

initialization block has been read

from memory and cleared by

writing a “1”. Writing a “0” has no

effect. IDON is cleared by RE-

SET or by setting the STOP bit.

INTR

Interrupt Flag indicates that one

or more of the following interrupt

causing conditions has occurred:

BABL, MISS, MERR, MPCO,

RCVCCO, RINT, TINT, IDON,

JAB or TXSTRT; and its associ-

ated mask bit is clear. If IENA = 1

and INTR is set, IRQ will be

active.

INTR is cleared automatically

when the condition that caused

interrupt is cleared.

INTR is read only. INTR is

cleared by RESET or by setting

the STOP bit.

IENA

Interrupt Enable allows IRQ to be

active if the Interrupt Flag is set. If

IENA = “0” then IRQ will be dis-

abled regardless of the state of

INTR.

IENA is set by writing a “1” and

cleared by writing a “0”. IENA is

cleared by RESET or by setting

the STOP bit.

RXON

Receive On indicates that the

Receive function is enabled.

RXON is set if DRX (CSR15.0) =

“0” after the START bit is set. If

INIT and START are set to-

gether, RXON will not be set until

after the initialization block has

been read in.

RXON is read only. RXON is

cleared by RESET or by setting

the STOP bit.

TXON

Transmit On indicates that the

Transmit function is enabled.

TXON is set if DTX (CSR15.1) =

“0” after the START bit is set. If

INIT and START are set to-

gether, TXON will not be set until

after the initialization block has

been read in.

TXON is read only. TXON is

cleared by RESET or by setting

the STOP bit.

TDMD

Transmit Demand, when set,

causes the Buffer Management

Unit to access the Transmit

Descriptor Ring without waiting

for

the

poll-time

counter

elapse. If TXON is not enabled,

TDMD bit will be reset and no

Transmit Descriptor Ring access

will occur. TDMD is required to

be set if the DPOLL bit in CSR4 is

set; setting TDMD while DPOLL

merely

hastens

the

PCnet-ISA controller’s response

to a Transmit Descriptor Ring En-

try.

TDMD is set by writing a “1”. Writ-

ing a “0” has no effect. TDMD will

be cleared by the Buffer Manage-

ment Unit when it fetches a

Transmit Descriptor. TDMD is

cleared by RESET or by setting

the STOP bit.

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