AM79C960KCW datasheet(57/127 Pages) AMD

57 / 127 page

P R E L I M I N A R Y

AMD

1-399

Am79C960

Receive FCS Checking

Reception and checking of the received FCS is per-

formed automatically by the PCnet-ISA controller. Note

that if the Automatic Pad Stripping feature is enabled,

the received FCS will be verified against the value com-

puted for the incoming bit stream including pad

characters, but it will not be passed to the host. If a FCS

error is detected, this will be reported by the CRC bit in

RMD1.

Receive Exception Conditions

Exception conditions for frame reception fall into two

distinct categories; those which are the result of normal

network operation, and those which occur due to abnor-

mal network and/or host related events.

Normal events which may occur and which are handled

autonomously by the PCnet-ISA controller are basically

collisions within the slot time and automatic runt packet

rejection. The PCnet-ISA controller will ensure that colli-

sions which occur within 512 bit times from the start of

reception (excluding preamble) will be automatically de-

leted from the receive FIFO with no host intervention.

The receive FIFO will delete any frame which is com-

posed of fewer than 64 bytes provided that the Runt

Packet Accept (RPA bit in CSR124) feature has not

been enabled. This criteria will be met regardless of

whether the receive frame was the first (or only) frame in

the FIFO or if the receive frame was queued behind a

previously received message.

Abnormal network conditions include:

s FCS errors

s Late collision

These should not occur on a correctly configured 802.3

network and will be reported if they do.

Host related receive exception conditions include MISS,

BUFF, and OFLO. These are described in the Receive

Descriptor section.

Loopback Operation

During loopback, the FCS logic can be allocated to the

receiver by setting the DXMTFCS bit in CSR15.

If DXMTFCS=0, the MAC Engine will calculate and ap-

pend the FCS to the transmitted message. In this

loopback configuration, the receive circuitry cannot de-

tect FCS errors if they occur.

If DXMTFCS=1, the last four bytes of the transmit mes-

sage must contain the (software generated) FCS

computed for the transmit data preceding it. The MAC

Engine will transmit the data without addition of an FCS

field, and the FCS will be calculated and verified at the

receiver.

The loopback facilities of the MAC Engine allow full op-

eration to be verified without disturbance to the network.

Loopback operation is also affected by the state of the

Loopback Control bits (LOOP, MENDECL, and INTL) in

CSR15. This affects whether the internal MENDEC is

considered part of the internal or external loopback

path.

When in the loopback mode(s), the multicast address

detection feature of the MAC Engine, programmed by

the contents of the Logical Address Filter (LADRF [63:0]

in CSR 8-11) can only be tested when DXMTFCS= 1, al-

locating the FCS generator to the receiver. All other

features operate identically in loopback as in normal op-

eration, such as automatic transmit padding and receive

pad stripping.

When performing an internal loopback, no frame will be

transmitted to the network. However, when the

PCnet-ISA controller is configured for internal loopback

the receiver will not be able to detect network traffic. AUI

external loopback tests will transmit frames onto the net-

work, and the PCnet-ISA controller will receive network

traffic while configured for external loopback. 10BASE-

T external loopback should never be used in a live

network. 10BASE-T external loopback provides a

means of looping Transmit data to the receive input

without asserting a collision. This mode allows a board

test to verify both the transmit and receive paths to the

10BASE-T connector. Unless the Runt Packet Accept

feature is enabled, all loopback frames must contain at

least 64 bytes of data.

LEDs

The PCnet-ISA controller’s LED control logic allows pro-

gramming of the status signals, which are displayed on

3 LED outputs. One LED (

LED0) is dedicated to display-

ing 10BASE-T Link Status. The status signals available

are Collision, Jabber, Receive, Receive Polarity (active

when receive polarity is okay), and Transmit. If more

than one status signal is enabled, they are ORed to-

gether. An optional pulse stretcher is available for each

programmable output. This allows emulation of the

TPEX (Am79C98) and TPEX+ (Am79C100) LED

outputs.

Signal

Behavior

LNKST

Active during Link OK

Not active during Link Down

RCV

Active while receiving data

RVPOL

Active during receive polarity is OK

Not active during reverse receive polarity

XMT

Active while transmitting data

AM79C960KCW датащи(PDF) 57 Page - Advanced Micro Devices

AM79C960KCW датащи(HTML) 57 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL