AM79C960KCW datasheet(25/127 Pages) AMD

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P R E L I M I N A R Y

AMD

1-367

Am79C960

PIN DESCRIPTION:

SHARED MEMORY MODE

ISA Interface

AEN

Address Enable

Input

This signal must be driven LOW when the bus performs

an I/O access to the device.

IOCHRDY

I/O Channel Ready

Output

When the PCnet-ISA controller is being accessed, a

HIGH on IOCHRDY indicates that valid data exists on

the data bus for reads and that data has been latched for

writes.

IOCS16

I/O Chip Select 16

Input/Output

When an I/O read or write operation is performed, the

PCnet-ISA controller will drive this pin LOW to indicate

that the chip supports a 16-bit operation at this address.

(If the motherboard does not receive this signal, then the

motherboard will convert a 16-bit access to two 8-bit ac-

cesses.) The

IOCS16 pin is also an input and must go

HIGH at least once after reset for the PCnet-ISA control-

ler to perform 16-bit I/O operations. If this pin is

grounded then the PCnet-ISA controller only performs

8-bit I/O operations.

The PCnet-ISA controller follows the IEEE P996 specifi-

cation that recommends this function be implemented

as a pure decode of SA0-9 and AEN, with no depend-

ency on

SMEMR, MEMR, MEMW, IOR, or IOW;

however, some PC/AT clone systems are not compat-

ible with this approach. For this reason, the PCnet-ISA

controller is recommended to be configured to run 8-bit

I/O on all machines. Since data is moved by memory cy-

cles there is virtually no performance loss incurred by

running 8-bit I/O and compatibility problems are virtually

eliminated. The PCnet-ISA controller can be configured

to run 8-bit-only I/O by disconnecting the

IOCS16 pin

from the ISA bus and tying the

IOCS16 pin to ground

instead.

IOR

I/O Read

Input

To perform an Input/Output Read operation on the de-

vice

IOR must be asserted. IOR is only valid if the AEN

signal is LOW and the external address matches the

PCnet-ISA controller ’s predefined I/O address location.

If valid,

IOR indicates that a slave read operation is to be

performed.

IOW

I/O Write

Input

To perform an Input/Output write operation on the de-

vice

IOW must be asserted. IOW is only valid if AEN

signal is LOW and the external address matches the

PCnet-ISA controller’s predefined I/O address location.

If valid,

IOW indicates that a slave write operation is to

be performed.

IRQ

Interrupt Request

Output

An attention signal which indicates that one or more of

the following status flags is set: BABL, MISS, MERR,

RINT, IDON or TXSTRT. All status flags have a mask bit

which allows for suppression of INTR assertion. These

flags have the following meaning:

BABL

Babble

RCVCCO

Receive Collision Count Overflow

JAB

Jabber

MISS

Missed Frame

MERR

Memory Error

MFCO

Missed Frame Count Overflow

RINT

Receive Interrupt

IDON

Initialization Done

TXSTRT

Transmit Start

MEMR

Memory Read

Input

MEMR goes LOW to perform a memory read operation.

MEMW

Memory Write

Input

MEMW goes LOW to perform a memory write

operation.

RESET

Reset

Input

When RESET is asserted HIGH, the PCnet-ISA control-

ler performs an internal system reset. RESET must be

held for a minimum of 10 XTAL1 periods before being

deasserted. While in a reset state, the PCnet-ISA con-

troller will tristate or deassert all outputs to predefined

reset levels. The PCnet-ISA controller resets itself upon

power-up.

SA0-9

System Address Bus

Input

This bus carries the address inputs from the system ad-

dress bus. Address data is stable during command

active cycle.

SBHE

System Bus High Enable

Input

This signal indicates the HIGH byte of the system data

bus is to be used. There is a weak pull-up resistor on this

pin. If the PCnet-ISA controller is installed in an 8-bit

only system like the PC/XT,

SBHE will always be HIGH

and the PCnet-ISA controller will perform only 8-bit op-

erations. There must be at least one LOW going edge on

this signal before the PCnet-ISA controller will perform

16-bit operations.

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