MPC8548ECPXATHC datasheet(148/151 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

148

Freescale Semiconductor

Document Revision History

24 Document Revision History

The following table provides a revision history for this hardware specification.

Table 88. Document Revision History

Rev.

Number

Date

Substantive Change(s)

02/2012

• Updated Section 21.2, “Thermal for Version 2.1.1, 2.1.2, and 2.1.3 Silicon FC-PBGA with Full Lid and

Version 3.1.x Silicon with Stamped Lid,” with version 3.0 silicon information.

• Added Figure 56, “Mechanical Dimensions and Bottom Surface Nomenclature of the FC-PBGA with

Stamped Lid.”

• Updated Table 87, “Part Numbering Nomenclature,” with version 3.0 silicon information.

• Removed Note from Section 5.1, “Power-On Ramp Rate”.

• Changed the Table 10 title to “Power Supply Ramp Rate”.

• Removed table 11.

• Updated the title of Section 21.2, “Thermal for Version 2.1.1, 2.1.2, and 2.1.3 Silicon FC-PBGA with

Full Lid and Version 3.1.x Silicon with Stamped Lid” to include Thermal Version 2.1.3 and Version 3.1.x

Silicon.

• Corrected the leaded Solder Ball composition in Table 70, “Package Parameters”

• Updated Table 87, “Part Numbering Nomenclature,” with Version 3.1.x silicon information.

• Updated the Min and Max value of TDO in the valid times row of Table 44, “JTAG AC Timing

Specifications (Independent of SYSCLK)1” from 4 and 25 to 2 and 10 respectively .

04/2011

• Added Section 14.1, “GPOUT/GPIN Electrical Characteristics.”

• Updated Table 71, “MPC8548E Pinout Listing,” Table 72, “MPC8547E Pinout Listing,” Table 73,

“MPC8545E Pinout Listing,” and Table 74, “MPC8543E Pinout Listing,” to reflect that the TDO signal

is not driven during HRSET* assertion.

• Updated Table 87, “Part Numbering Nomenclature” with Ver. 2.1.3 silicon information.

09/2010

• In Table 37, “MII Management AC Timing Specifications, modified the fifth row from “MDC to MDIO

delay tMDKHDX (16 × tptb_clk × 8) – 3 — (16 × tptb_clk × 8) + 3” to “MDC to MDIO delay tMDKHDX

(16 × tCCB × 8) – 3 — (16 × tCCB × 8) + 3.”

• Updated Figure 55, “Mechanical Dimensions and Bottom Surface Nomenclature of the HiCTE

FC-CBGA and FC-PBGA with Full Lid and figure notes.

12/2009

• In Section 5.1, “Power-On Ramp Rate” added explanation that Power-On Ramp Rate is required to

avoid falsely triggering ESD circuitry.

•In Table 13 changed required ramp rate from 545 V/s for MVREF and VDD/XVDD/SVDD to 3500 V/s

for MVREF and 4000 V/s for VDD.

•In Table 13 deleted ramp rate requirement for XVDD/SVDD.

•In Table 13 footnote 1 changed voltage range of concern from 0–400 mV to 20–500mV.

•In Table 13 added footnote 2 explaining that VDD voltage ramp rate is intended to control ramp rate of

AVDD pins.

10/2009

• In Table 27, “GMII Receive AC Timing Specifications,” changed duty cycle specification from 40/60 to

35/75 for RX_CLK duty cycle.

• Updated tMDKHDX in Table 37, “MII Management AC Timing Specifications.”

• Added a reference to Revision 2.1.2.

• Updated Table 55, “MII Management AC Timing Specifications.”

• Added Section 5.1, “Power-On Ramp Rate.”

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