MPC8548ECPXATHC datasheet(144/151 Pages) FREESCALE

144 / 151 page

MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

144

Freescale Semiconductor

System Design Information

•

SD_REF_CLK

NOTE

It is recommended to power down the unused lane through SRDSCR1[0:7]

receiver output in a fixed state) that maps to SERDES lane 0 to lane 7

accordingly.

Pins V28 and M26 must be tied to XVDD. Pins V27 and M25 must be tied to GND through a 300-

resistor.

22.11 Guideline for PCI Interface Termination

PCI termination if PCI 1 or PCI 2 is not used at all.

Option 1

If PCI arbiter is enabled during POR:

•

All AD pins are driven to the stable states after POR. Therefore, all ADs pins can be floating.

•

All PCI control pins can be grouped together and tied to OVDD through a single 10-k resistor.

•

It is optional to disable PCI block through DEVDISR register after POR reset.

Option 2

If PCI arbiter is disabled during POR:

•

All AD pins are in the input state. Therefore, all ADs pins need to be grouped together and tied to

OVDD through a single (or multiple) 10-k resistor(s).

•

All PCI control pins can be grouped together and tied to OVDD through a single 10-k resistor.

•

It is optional to disable PCI block through DEVDISR register after POR reset.

22.12 Guideline for LBIU Termination

If the LBIU parity pins are not used, the following is the termination recommendation:

•

For LDP[0:3]—tie them to ground or the power supply rail via a 4.7-k

 resistor.

•

For LPBSE—tie it to the power supply rail via a 4.7-k

 resistor (pull-up resistor).

MPC8548ECPXATHC датащи(PDF) 144 Page - Freescale Semiconductor, Inc