AMC7812SPAPR datasheet(9/92 Pages) TI

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AMC7812

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SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013

PIN DESCRIPTIONS (continued)

PIN (QFN / HTQFP)

DESCRIPTION

NO.

NAME

DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-0 pin enter

a clear state, the DAC Latch is loaded with predefined code, and the output is set to the corresponding level.

DAC-CLR-0

However, the DAC-Data Register does not change. When the DAC goes back to normal operation, the DAC

Latch is loaded with the previous data from the DAC-Data Register and the output returns to the previous level,

regardless of the status of the SLDAC-n bit. When this pin is high, the DACs are in normal operation.

DAC5-OUT

DAC4-OUT

Output of DAC channels 3, 4, and 5

DAC3-OUT

AGND4

Analog ground

AGND3

Positive analog power for DAC0-OUT, DAC1-OUT, DAC2-OUT, DAC3-OUT, DAC4-OUT, DAC5-OUT, must be

AVCC2

tied to AVCC1

DAC2-OUT

DAC1-OUT

Output of DAC channels 0, 1, and 2

DAC0-OUT

D2–/GPIO-6

Remote sensor D2 negative input when D2 enabled; GPIO-6 when D2 disabled. Pull-up required for output.

D2+/GPIO-7

Remote sensor D2 positive input when D2 enabled; GPIO-7 when D2 disabled. Pull-up required for output.

D1–/GPIO4

Remote sensor D1 negative input when D1 enabled; GPIO-6 when D1 disabled. Pull-up required for output.

D1+/GPIO-5

Remote sensor D1 positive input when D1 enabled; GPIO-7 when D1 disabled. Pull-up required for output.

External ADC reference input when external VREF is used to drive ADC. Compensation capacitor connection

ADC-REF-IN/CMP

(connect 4.7µF capacitor between this pin and AGND) when Internal VREF is used to drive ADC.

ADC-GND

ADC ground. Must be connected to AGND.

33-

Analog inputs of channel 0 to 15. CH4 to CH15 are single-ended. CH0, CH1, CH2, and CH3 can be

CH0 to CH15

programmed as differential or single-ended.

AVDD1

Positive analog power supply

AVDD2

DAC6-OUT

DAC7-OUT

Output of DAC channels 6, 7, and 8

DAC8-OUT

AGND1

Analog ground

AGND2

Positive analog power for DAC6-OUT, DAC7-OUT, DAC8-OUT, DAC9-OUT, DAC10-OUT, DAC11-OUT, must

AVCC1

be tied to AVCC2

REF-OUT

Internal reference output

REF-DAC

DAC reference Input

DAC9-OUT

DAC10-OUT

Output of DAC channels 9, 10, and 11

DAC11-OUT

Global alarm. Open drain output. External 10k

Ω pull-up resistor required. This pin goes low (active) when one

ALARM

(or more) of the analog channels are out of range.

DAC clear control signal, digital input, active low. When low, all DACs associated with the DAC-CLR-1 pin enter

a clear state, the DAC Latch is loaded with predefined code, and the output is set to the corresponding level.

DAC-CLR-1

However, the DAC-Data Register does not change. When the DAC goes back to normal operation, the DAC

Latch is loaded with the previous data from the DAC-Data Register and the output returns to the previous level,

regardless of the status of the SLDAC-n bit. When this pin is high, the DACs are in normal operation.

DGND2

Digital ground

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