AMC7812SPAPR datasheet(42/92 Pages) TI

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AMC7812

SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013

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Synchronous Load, Asynchronous Load, and Output Updating

The SLDA-n (synchronous load) bit of the DAC Configuration Register determines the DAC updating mode, as

shown in Table 5. When SLDA-n is cleared to '0', asynchronous mode is active, the DAC Latch updates

immediately after writing to the DAC-n-Data Register, and the output of DAC-n changes accordingly.

Table 5. DAC-n Output Update Summary for Manual Mode Update

SLDA-n BIT

WRITING TO ILDAC BIT

OPERATION

Update DAC-n individually. The DAC-n Latch and DAC-n output are immediately

Don't care

updated after writing to the DAC-n-Data Register.

Simultaneously update all DACs by internal trigger. Writing '1' to the ILDAC bit

generates an internal load DAC trigger signal that updates the DAC-n Latches and

DAC-n outputs with the contents of the corresponding DAC-n-Data Register.

When the SLDA-n bit is set to '1', synchronous mode is selected. The value of the DAC-n-Data Register is

transferred to the DAC-n Latch only after an active DAC synchronous loading signal (ILDAC) occurs, which

immediately updates the DAC-n output. Under synchronous loading operation, writing data into a DAC-n-Data

until the synchronous load signal occurs.

The DAC synchronous load is triggered by writing '1' to the ILDAC bit in AMC Configuration Register 0. When

this DAC synchronous load signal occurs, all DACs with the SLDA-n bit set to '1' are simultaneously updated with

the value of the corresponding DAC-n-Data Register. By setting the SLDA-n bit properly, several DACs can be

updated at the same time. For example, to update DAC0 and DAC1 synchronously, set bits SLDA-0 and SLDA-1

to '1' first, and then write the proper values into the DAC-0 and DAC-1-Data Registers, respectively. After this

presetting, set the ILDAC bit = '1' to simultaneously load DAC0 and DAC1. The outputs of DAC0 and DAC1

change at the same time.

The AMC7812 updates the DAC Latch only if it has been accessed since the last time ILDAC was issued,

thereby eliminating any unnecessary glitch. Any DAC channels that have not been accessed are not reloaded

again. When the DAC Latch is updated, the corresponding output changes to the new level immediately.

NOTE

When DACs are cleared by an external DAC-CLR-n or by the internal CLR bit, the DAC

Latch is loaded with the predefined value of the DAC-n-CLR-Setting Register and the

output is set to the corresponding level immediately, regardless of the SLDA-n bit value.

However, the DAC Data Register does not change.

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