AMC7812SPAPR datasheet(31/92 Pages) TI

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ToShift

ADC

ADC-0

Data

ADC-0

Temporary

Out-of-Limit

Alarm

ADC-7

Data

ADC-7

Temporary

ADC-15

Data

ADC-15

Temporary

DAVFBit

DAV

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH9

CH10

CH11

CH12

CH13

CH14

CH15

CONVERT

(ExternalTrigger)

ICONV

(Internal

Trigger)

Input

Range

Selection

AMC7812

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SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013

When any of following events occur, the current conversion cycle stops immediately:

•

A new trigger is issued.

•

The conversion mode changes.

•

Either ADC channel register is rewritten.

•

Any of the analog input threshold registers is rewritten.

When a new external or internal trigger activates, the ADC starts a new conversion cycle.

The internal trigger should not be issued at the same time the conversion mode is changed. If a '1' is

simultaneously written to the ICONV bit when changing the CMODE bit to '0' or '1', the current conversion stops

and immediately returns to the wait for ADC trigger state.

Double-Buffered ADC Data Registers

The host can access all sixteen, double-buffered ADC Data Registers, as shown in Figure 83. The conversion

result from the analog input with channel address n (where n = 0 to 15) is stored in the ADC-n-Data Register.

When the conversion of an individual channel is completed, the data are immediately transferred into the

corresponding ADC-n temporary (TMPRY) register, the first stage of the data buffer. When the conversion of the

last channel completes, all data in the ADC-n TMPRY Registers are simultaneously transferred into the

corresponding ADC-n-Data Registers, the second stage of the data buffer. However, if a data transfer is in

progress between any ADC-n-Data Register and the AMC Shift Register, all ADC-n-Data Registers are not

updated until the data transfer is complete. The conversion result from channel address n is stored in the ADC-n-

Data Register. For example, the result from channel 0 is stored in the ADC-0-Data Register, and the result from

channel 3 is stored in the ADC-3-Data Register.

Figure 83. Double-Buffered ADC Structure

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