AMC7812SPAPR datasheet(69/92 Pages) TI

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AMC7812

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SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013

Table 21. Alarm Control Register (continued)

BIT

NAME

DEFAULT

R/W

DESCRIPTION

D2 fail alarm enable bit.

If EALR-D2-FAIL = '1', the D2-Fail alarm is enabled. When D2 fails, the D2-FAIL-ALR bit is

EALR-D2-FAIL

R/W

set ('1'), the ALARM pin goes low (if enabled).

If EALR-D2-FAIL = '0', the D2-FAIL alarm is masked. When D2 fails, the ALARM pin does

not go low, but the D2-FAIL-ALR bit is set.

Alarm latch disable bit.

When ALARM-LATCH-DIS = '1', the Status Register bits are not latched. When the alarm

condition subsides, the alarm bits are cleared regardless of whether the Status Register

ALARM-

has been read or not.

R/W

LATCH-DIS

When ALARM-LATCH-DIS = '0', the Status Register bits are latched. When an alarm

occurs, the corresponding alarm bit is set ('1'). The alarm bit remains '1' until the error

condition subsides and the Status Register is read. Before reading, the alarm bit is not

cleared ('0') even if the alarm condition disappears.

—

Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

—

Reserved. Writing to this bit causes no change. Reading this bit returns '0'.

STATUS REGISTER (Read Only, Address = 4Fh, Default = 0000h)

The AMC7812 continuously monitors all analog inputs and temperatures during normal operation. When any

input is out of the specified range N consecutive times, the corresponding alarm bit is set ('1'). If the input returns

to the normal range before N consecutive times, the corresponding alarm bit remains clear ('0'). This

configurations avoids any false alarms.

When an alarm status occurs, the corresponding alarm bit is set ('1'). When the ALARM-LATCH-DIS bit in the

Alarm Control Register is cleared ('0'), the ALARM pin is latched. Whenever an alarm status bit is set, it remains

set until the event that caused it is resolved and the Status Register is read. Reading the Status Registers clears

the alarm status bit. The alarm bit can only be cleared by reading the Status Register after the event is resolved,

or by hardware reset, software reset, or power-on reset. All alarm status bits are cleared when reading the Status

unless otherwise noted.

When the ALARM-LATCH-DIS bit in the Alarm Control Register is set ('1'), the ALARM pin is not latched. The

alarm bit goes to '0' when the error condition subsides, regardless of whether the bit is read or not.

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