AMC7812SPAPR datasheet(79/92 Pages) TI

79 / 92 page

AMC7812

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SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013

POWER-DOWN REGISTER (Read/Write, Address = 6Bh, Default = 0000h)

After power-on or reset, all bits in the Power-Down Register are cleared to '0', and all the components controlled

by this register are either powered-down or off. The Power-Down Register allows the host to manage the

AMC7812 power dissipation. When not required, the ADC, the reference buffer amplifier, and any of the DACs

can be put into an inactive low-power mode to reduce current drain from the supply. The bits in the Power-Down

MSB

LSB

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

PDAC

PADC

PREF

Bit 14

PADC: Power-down mode control bit.

If PADC = '1', the ADC is in normal operating mode.

If PADC = '0', the ADC is inactive in low-power mode.

Bit 13

PREF: Internal reference in power-down mode control bit.

If PREF = '1', the reference buffer amplifier is powered on.

If PREF = '0', the reference buffer amplifier is inactive in low-power mode.

Bits[12:1]

PDACn: DACn power-down control bit.

If PDACn = '1', DACn is in normal operating mode.

If PDACn = '0', DACn is inactive in low-power mode and its output buffer amplifier is in a Hi-Z state. The output pin of

DACn is internally switched from the buffer output to the analog ground through an internal resistor.

Device ID Register (Read-Only, Address = 6Ch, Default = 1220h)

Model and revision information.

Software Reset Register (Read/Write, Address = 7Ch, Default = NA)

The Software Reset Register resets all registers to default values, except for the DAC Data Register, DAC Latch,

and DAC Clear Register. The software reset is similar to a hardware reset, which resets all registers including

the DAC Data Register, DAC Latch, and DAC Clear Register. After a software reset, make sure that the DAC

Data Register, DAC latch, and DAC Clear Register are set to the desired values before the DAC is powered on.

SPI Mode

In SPI Mode, writing 6600h to this register forces the device reset.

I2C Mode

Writing to this register (with any data) forces the device to perform a software reset. Reading this register returns

an undefined value that must be ignored. Note that this register is 8-bit, instead of 16-bit. Both reading from and

writing to this register are single-byte operations. Writing data to the Software Reset Register in I2C Mode is

shown in the following steps:

1. The master device asserts a start condition.

2. The master then sends the 7-bit AMC7812 slave address followed by a zero for the direction bit, indicating a

write operation.

3. The AMC7812 asserts an acknowledge signal on SDA.

4. The master sends register address 7Ch.

5. The AMC7812 asserts an acknowledge signal on SDA.

6. The master sends a data byte.

7. The AMC7812 asserts an acknowledge signal on SDA.

8. The master asserts a stop condition to end the transaction.

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