AMC7812SPAPR datasheet(65/92 Pages) TI

65 / 92 page

AMC7812

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SBAS513E – JANUARY 2011 – REVISED SEPTEMBER 2013

DAC-n-DATA REGISTERS (Read/Write, Addresses = 33h to 3Eh, Default 0000h)

Each DAC has a DAC data register to store the data [DAC11:DAC0] that is loaded into the DAC Latches.

MSB

LSB

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

D11

D10

Bits[11:0]

DAC data.

DAC-n-CLR-SETTING REGISTERS (Read/Write, Addresses = 3Fh to 4Ah, Default 0000h)

Each DAC has a DAC-CLR-Setting Register to store the data to be loaded into the DAC Latch when the DAC is

cleared.

MSB

LSB

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

DCLR

GPIO REGISTER (Read/Write, Address = 4Bh, Default = 00FFh)

MSB

LSB

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

GPIO-

For write operations, the GPIO pin operates as an output. Writing a '1' to the GPIO-n bit sets the GPIO-n pin to

high impedance. Writing a '0' sets the GPIO-n pin to logic low. An external pull-up resistor is required when using

the GPIO pin as an output.

For read operations, the GPIO pin operates as an input. Read the GPIO-n bit to receive the status of the GPIO-n

pin. Reading a '0' indicates that the GPIO-n pin is low; reading a '1' indicates that the GPIO-n pin is high.

After power-on reset, or any forced hardware or software reset, the GPIO-n bit is set to '1' and is in a high-

impedance state.

When D1 is enabled, GPIO-4 and GPIO-5 are ignored.

When D2 is enabled, GPIO-6 and GPIO-7 are ignored.

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