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JS28F128P30TF75A датащи(PDF) 39 Page - Micron Technology |
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JS28F128P30TF75A датащи(HTML) 39 Page - Micron Technology |
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39 / 90 page ![]() Datasheet Apr 2010 39 Order Number:208033-02 P30-65nm SBC 11.2.6 WAIT Delay (RCR.8) The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during synchronous burst reads. WAIT can be asserted either during or one data cycle before valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle before valid data (default). When WD is cleared, WAIT is deasserted during valid data. 11.2.7 Burst Sequence (RCR.7) The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst sequence is supported. Table 17 shows the synchronous burst sequence for all burst lengths, as well as the effect of the Burst Wrap (BW) setting. Figure 13: Data Hold Timing Valid Output Valid Output Valid Output Valid Output Valid Output CLK [C] D[15:0] [Q] D[15:0] [Q] 2 CLK Data Hold 1 CLK Data Hold Table 17: Burst Sequence Word Ordering (Sheet 1 of 2) Start Addr. (DEC) Burst Wrap (RCR.3) Burst Addressing Sequence (DEC) 4-Word Burst (BL[2:0] = 0b001) 8-Word Burst (BL[2:0] = 0b010) 16-Word Burst (BL[2:0] = 0b011) Continuous Burst (BL[2:0] = 0b111) 0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-… 1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5…15-0 1-2-3-4-5-6-7-… 2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6…15-0-1 2-3-4-5-6-7-8-… 3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7…15-0-1-2 3-4-5-6-7-8-9-… 40 4-5-6-7-0-1-2-3 4-5-6-7-8…15-0-1-2-3 4-5-6-7-8-9-10… 50 5-6-7-0-1-2-3-4 5-6-7-8-9…15-0-1-2-3- 4 5-6-7-8-9-10-11… 60 6-7-0-1-2-3-4-5 6-7-8-9-10…15-0-1-2- 3-4-5 6-7-8-9-10-11-12-… 70 7-0-1-2-3-4-5-6 7-8-9-10…15-0-1-2-3- 4-5-6 7-8-9-10-11-12-13… 14 0 14-15-0-1-2…12-13 14-15-16-17-18-19-20- … 15 0 15-0-1-2-3…13-14 15-16-17-18-19-20-21- … 0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-… |
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