JS28F128P30TF75A datasheet(38/90 Pages) MICRON

38 / 90 page

P30-65nm SBC

Datasheet

Apr 2010

Order Number: 208033-02

Table 15: End of Wordline Data and WAIT state Comparison

11.2.4

WAIT Polarity (RCR.10)

The WAIT Polarity bit (WP), RCR.10 determines the asserted level (VOH or VOL) of WAIT.

When WP is set, WAIT is asserted high. When WP is cleared, WAIT is asserted low

(default). WAIT changes state on valid clock edges during active bus cycles (CE#

asserted, OE# asserted, RST# deasserted).

11.2.5

Data Output Configuration (RCR.9)

The Data Output Configuration (DOC) bit, RCR.9 determines whether a data word

remains valid on the data bus for one or two clock cycles. This period of time is called

the “data cycle”. When DOC is set, output data is held for two clocks (default). When

DOC is cleared, output data is held for one clock (see Figure 13, “Data Hold Timing” on

page 39). The processor’s data setup time and the flash memory’s clock-to-data output

delay should be considered when determining whether to hold output data for one or

two clocks. A method for determining the Data Hold configuration is shown below:

To set the device at one clock data hold for subsequent reads, the following condition

must be satisfied:

tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)

tDATA = Data set up to Clock (defined by CPU)

For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming

tCHQV = 20 ns and tDATA = 4 ns. Applying these values to the formula above:

20 ns + 4 ns ≤ 25 ns

The equation is satisfied and data will be available at every clock period with data hold

setting at one clock. If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of

2 clock periods must be used.

Latency Count

P30-130nm

P30-65nm SBC

Data States

WAIT States

Data States

WAIT States

Not Supported

0 to 1

Not Supported

0 to 2

0 to 3

0 to 4

0 to 5

0 to 6

Table 16: WAIT Functionality Table

Condition

WAIT

Notes

CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’

High-Z

CE# =’0’, OE# = ‘0’

Active

Synchronous Array Reads

Active

Synchronous Non-Array Reads

Active

All Asynchronous Reads

Deasserted

All Writes

High-Z

1,2

Notes:

Active: WAIT is asserted until data becomes valid, then deasserts.

When OE# = VIH during writes, WAIT = High-Z.

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