JS28F128P30TF75A datasheet(26/90 Pages) MICRON

26 / 90 page

P30-65nm SBC

Datasheet

Apr 2010

Order Number: 208033-02

8.3.1

BEFP Requirements and Considerations

Note:

Word buffer boundaries in the array are determined by A[8:1] (0x00 through 0xFF). The alignment start point is A[8:1] =

0x000.

Notes:

Some degradation in performance may occur is this limit is exceeded, but the internal algorithm continues to work

properly.

If the internal address counter increments beyond the block’s maximum address, addressing wraps around to the

beginning of the block.

If the number of words is less than 256, remaining locations must be filled with 0xFFFF.

8.3.2

BEFP Setup Phase

After receiving the BEFP Setup and Confirm command sequence, Status Register bit

SR.7 (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A

delay before checking SR.7 is required to allow the WSM enough time to perform all of

its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR.4

is set and BEFP operation terminates. If the block was found to be locked, SR.1 is also

set. SR.3 is set if the error occurred due to an incorrect VPP level.

Note:

Reading from the device after the BEFP Setup and Confirm command sequence outputs

Status Register data. Do not issue the Read Status Register command; it will be

interpreted as data to be loaded into the buffer.

8.3.3

BEFP Program/Verify Phase

After the BEFP Setup Phase has completed, the host programming system must check

SR[7,0] to determine the availability of the write buffer for data streaming. SR.7

cleared indicates the device is busy and the BEFP program/verify phase is activated.

SR.0 indicates the write buffer is available.

Table 10: BEFP Requirements

Parameter/Issue

Requirement

Notes

Case Temperature

TC = 30°C ± 10°C

VCC

Nominal Vcc

VPP

Driven to VPPH

Setup and Confirm

Target block must be unlocked before issuing the BEFP Setup and Confirm commands.

Programming

The first-word address (WA0) of the block to be programmed must be held constant

from the setup phase through all data streaming into the target block, until transition

to the exit phase is desired.

Buffer Alignment

WA0 must align with the start of an array buffer boundary.

Table 11: BEFP Considerations

Parameter/Issue

Requirement

Notes

Cycling

For optimum performance, cycling must be limited below 50 erase cycles per block.

Programming blocks

BEFP programs one block at a time; all buffer data must fall within a single block.

Suspend

BEFP cannot be suspended.

Programming the flash

memory array

Programming to the flash memory array can occur only when the buffer is full.

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