MC68331TS datasheet(58/84 Pages) FREESCALE

58 / 84 page

MC68331TS/D

5.4.2 QSPI Registers

The programmer's model for the QSPI submodule consists of the QSM global and pin control registers,

four QSPI control registers, one status register, and the 80-byte QSPI RAM.

The CPU can read and write to registers and RAM. The four control registers must be initialized before

the QSPI is enabled to ensure defined operation. SPCR1 should be written last because it contains

QSPI enable bit SPE. Asserting this bit starts the QSPI. The QSPI control registers are reset to a de-

fined state and can then be changed by the CPU. Reset values are shown below each register.

Refer to the following memory map of the QSPI.

Writing a different value into any control register except SPCR2 while the QSPI is enabled disrupts op-

eration. SPCR2 is buffered to prevent disruption of the current serial transfer. After completion of the

current serial transfer, the new SPCR2 values become effective.

Writing the same value into any control register except SPCR2 while the QSPI is enabled has no effect

on QSPI operation. Rewriting NEWQP in SPCR2 causes execution to restart at the designated location.

SPCR0 contains parameters for configuring the QSPI before it is enabled. The CPU can read and write

this register. The QSM has read-only access.

Pin Names

Mnemonics

Mode

Function

Master In Slave Out

MISO

Master

Slave

Serial Data Input to QSPI

Serial Data Output from QSPI

Master Out Slave In

MOSI

Master

Slave

Serial Data Output from QSPI

Serial Data Input to QSPI

Serial Clock

SCK

Master

Slave

Clock Output from QSPI

Clock Input to QSPI

Peripheral Chip Selects

PCS[3:1]

Master

Select Peripherals

Peripheral Chip Select

Slave Select

PCS0

Master

Slave

Selects Peripheral

Causes Mode Fault

Initiates Serial Transfer

Address

Name

Usage

$YFFC18

SPCR0

QSPI Control Register 0

$YFFC1A

SPCR1

QSPI Control Register 1

$YFFC1C

SPCR2

QSPI Control Register 2

$YFFC1E

SPCR3

QSPI Control Register 3

$YFFC1F

SPSR

QSPI Status Register

$YFFD00

RAM

QSPI Receive Data (16 Words)

$YFFD20

RAM

QSPI Transmit Data (16 Words)

$YFFD40

RAM

QSPI Command Control (8 Words)

SPCR0 — QSPI Control Register 0

$YFFC18

MSTR

WOMQ

BITS

CPOL

CPHA

SPBR

RESET:

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68331TS датащи(PDF) 58 Page - Freescale Semiconductor, Inc

MC68331TS датащи(HTML) 58 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

датащи скачать

ссылки URL