MC68331TS datasheet(23/84 Pages) FREESCALE

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MC68331TS/D

3.3.2 Clock Synthesizer Operation

A voltage controlled oscillator (VCO) generates the system clock signal. A portion of the clock signal is

fed back to a divider/counter. The divider controls the frequency of one input to a phase comparator.

The other phase comparator input is a reference signal, either from the internal oscillator or from an

external source. The comparator generates a control signal proportional to the difference in phase be-

tween its two inputs. The signal is low-pass filtered and used to correct VCO output frequency.

The synthesizer locks when VCO frequency is identical to reference frequency. Lock time is affected by

the filter time constant and by the amount of difference between the two comparator inputs. Whenever

comparator input changes, the synthesizer must re-lock. Lock status is shown by the SLOCK bit in SYN-

CR.

The MCU does not come out of reset state until the synthesizer locks. Crystal type, characteristic fre-

quency, and layout of external oscillator circuitry affect lock time.

The low-pass filter requires an external low-leakage capacitor, typically 0.1

µF, connected between the

XFC and VDDSYN pins.

VDDSYN is used to power the clock circuits. A separate power source increases MCU noise immunity

and can be used to run the clock when the MCU is powered down. Use a quiet power supply as the

VDDSYN source, since PLL stability depends on the VCO, which uses this supply. Place adequate ex-

ternal bypass capacitors as close as possible to the VDDSYN pin to ensure stable operating frequency.

When the clock synthesizer is used, control register SYNCR determines operating frequency and vari-

ous modes of operation. SYNCR can be read only when the processor is operating at the supervisor

privilege level.

The SYNCR X bit controls a divide by two prescaler that is not in the synthesizer feedback loop. Setting

X doubles clock speed without changing VCO speed. There is no VCO relock delay. The SYNCR W bit

controls a 3-bit prescaler in the feedback divider. Setting W increases VCO speed by a factor of four.

The SYNCR Y field determines the count modulus for a modulo 64 down counter, causing it to divide

by a value of Y

+ 1. When either W or Y value changes, there is a VCO relock delay.

Clock frequency is determined by SYNCR bit settings as follows:

FSYSTEM = FREFERENCE [4(Y + 1)(2

2W +X)]

In order for the device to perform correctly, the clock frequency selected by the W, X, and Y bits must

be within the limits specified for the MCU. The VCO frequency is twice the system clock frequency if X

= 1 or four times the system clock frequency if X = 0.

The reset state of SYNCR ($3F00) produces a modulus-64 count.

3.3.3 Clock Control

The clock control circuits determine system clock frequency and clock operation under special circum-

stances, such as following loss of synthesizer reference or during low-power operation. Clock source is

determined by the logic state of the MODCLK pin during reset.

SYNCR —Clock Synthesizer Control Register

$YFFA04

EDIV

SLIMP

SLOCK RSTEN

STSIM

STEXT

RESET:

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