MC68331TS datasheet(26/84 Pages) FREESCALE

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MC68331TS/D

3.4.4 Address Strobe

AS is a timing signal that indicates the validity of an address on the address bus and the validity of many

control signals. It is asserted one-half clock after the beginning of a bus cycle.

3.4.5 Data Bus

Data bus signals DATA[15:0] make up a bidirectional, non-multiplexed parallel bus that transfers data

to or from the MCU. A read or write operation can transfer 8 or 16 bits of data in one bus cycle. During

a read cycle, the data is latched by the MCU on the last falling edge of the clock for that bus cycle. For

a write cycle, all 16 bits of the data bus are driven, regardless of the port width or operand size. The

MCU places the data on the data bus one-half clock cycle after AS is asserted in a write cycle.

3.4.6 Data Strobe

Data strobe (DS) is a timing signal. For a read cycle, the MCU asserts DS to signal an external device

to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle,

DS signals an external device that data on the bus is valid. The MCU asserts DS one full clock cycle

after the assertion of AS during a write cycle.

3.4.7 Bus Cycle Termination Signals

During bus cycles, external devices assert the data transfer and size acknowledge signals (DSACK1

and DSACK0). During a read cycle, the signals tell the MCU to terminate the bus cycle and to latch data.

During a write cycle, the signals indicate that an external device has successfully stored data and that

the cycle can end. These signals also indicate to the MCU the size of the port for the bus cycle just com-

pleted. (Refer to 3.4.9 Dynamic Bus Sizing.)

The bus error (BERR) signal is also a bus cycle termination indicator and can be used in the absence

of DSACK1 and DSACK0 to indicate a bus error condition. It can also be asserted in conjunction with

these signals, provided it meets the appropriate timing requirements. The internal bus monitor can be

used to generate the BERR signal for internal and internal-to-external transfers. When BERR and HALT

are asserted simultaneously, the CPU takes a bus error exception.

Autovector signal (AVEC) can terminate external IRQ pin interrupt acknowledge cycles. AVEC indicates

that the MCU will internally generate a vector number to locate an interrupt handler routine. If it is con-

tinuously asserted, autovectors will be generated for all external interrupt requests. AVEC is ignored

during all other bus cycles.

3.4.8 Data Transfer Mechanism

The MCU architecture supports byte, word, and long-word operands, allowing access to 8- and 16-bit

data ports through the use of asynchronous cycles controlled by the data transfer and size acknowledge

inputs (DSACK1 and DSACK0).

3.4.9 Dynamic Bus Sizing

The MCU dynamically interprets the port size of the addressed device during each bus cycle, allowing

operand transfers to or from 8- and 16-bit ports. During an operand transfer cycle, the slave device sig-

nals its port size and indicates completion of the bus cycle to the MCU through the use of the DSACK0

and DSACK1 inputs, as shown in the following table.

Table 10 Effect of DSACK Signals

DSACK1

DSACK0

Result

Insert Wait States in Current Bus Cycle

Complete Cycle —Data Bus Port Size is 8 Bits

Complete Cycle —Data Bus Port Size is 16 Bits

Reserved

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