MC68331TS datasheet(38/84 Pages) FREESCALE

38 / 84 page

MC68331TS/D

3.7.3 Reset Timing

The RESET input must be asserted for a specified minimum period in order for reset to occur. External

RESET assertion can be delayed internally for a period equal to the longest bus cycle time (or the bus

monitor time-out period) in order to protect write cycles from being aborted by reset. While RESET is

asserted, SIM pins are either in a disabled high-impedance state or are driven to their inactive states.

When an external device asserts RESET for the proper period, reset control logic clocks the signal into

an internal latch. The control logic drives the RESET pin low for an additional 512 CLKOUT cycles after

it detects that the RESET signal is no longer being externally driven, to guarantee this length of reset

to the entire system.

If an internal source asserts a reset signal, the reset control logic asserts RESET for a minimum of 512

cycles. If the reset signal is still asserted at the end of 512 cycles, the control logic continues to assert

RESET until the internal reset signal is negated.

After 512 cycles have elapsed, the reset input pin goes to an inactive, high-impedance state for 10 cy-

cles. At the end of this 10-cycle period, the reset input is tested. When the input is at logic level one,

reset exception processing begins. If, however, the reset input is at logic level zero, the reset control

logic drives the pin low for another 512 cycles. At the end of this period, the pin again goes to high-

impedance state for 10 cycles, then it is tested again. The process repeats until RESET is released.

3.7.4 Power-On Reset

When the SIM clock synthesizer is used to generate the system clock, power-on reset involves special

circumstances related to application of system and clock synthesizer power. Regardless of clock

source, voltage must be applied to clock synthesizer power input pin VDDSYN in order for the MCU to

operate. The following discussion assumes that VDDSYN is applied before and during reset. This mini-

mizes crystal start-up time. When VDDSYN is applied at power-on, start-up time is affected by specific

crystal parameters and by oscillator circuit design. VDD ramp-up time also affects pin state during reset.

During power-on reset, an internal circuit in the SIM drives the internal (IMB) and external reset lines.

The circuit releases the internal reset line as VDD ramps up to the minimum specified value, and SIM

pins are initialized. When VDD reaches the specified minimum value, the clock synthesizer VCO begins

operation. Clock frequency ramps up to the specified limp mode frequency. The external RESET line

remains asserted until the clock synthesizer PLL locks and 512 CLKOUT cycles elapse.

Table 19 Module Pin Functions

Module

Pin Mnemonic

Function

CPU32

DSI/IFETCH

DSO/IPIPE

BKPT/DSCLK

GPT

PGP7/IC4/OC5

Discrete Input

PGP[6:3]/OC[4:1]

Discrete Input

PGP[2:0]/IC[3:1]

Discrete Input

PAI

Discrete Input

PCLK

Discrete Input

PWMA, PWMB

Discrete Output

QSM

PQS7/TXD

Discrete Input

PQS[6:4]/PCS[3:1]

Discrete Input

PQS3/PCS0/SS

Discrete Input

PQS2/SCK

Discrete Input

PQS1/MOSI

Discrete Input

PQS0/MISO

Discrete Input

RXD

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68331TS датащи(PDF) 38 Page - Freescale Semiconductor, Inc

MC68331TS датащи(HTML) 38 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

датащи скачать

ссылки URL