MC68331TS datasheet(32/84 Pages) FREESCALE

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MC68331TS/D

ADDR[23:11] —Base Address Field

This field sets the starting address of a particular address space. The address compare logic uses only

the most significant bits to match an address within a block. The value of the base address must be a

multiple of block size. Base address register diagrams show how base register bits correspond to ad-

dress lines.

3.5.4 Option Registers

The option registers contain eight fields that determine timing of and conditions for assertion of chip-

select signals. For a chip-select signal to be asserted, all bits in the base address register must match

the corresponding internal upper address lines, and all conditions specified in the option register must

be satisfied. These conditions also apply to providing DSACK or autovector support.

CSORBT, the option register for CSBOOT, contains special reset values that support bootstrap opera-

tions from peripheral memory devices.

The following bit descriptions apply to both CSORBT and CSOR[10:0] option registers.

MODE —Asynchronous/Synchronous Mode

0 = Asynchronous mode selected (chip-select assertion determined by internal or external bus con-

trol signals)

1 = Synchronous mode selected (chip-select assertion synchronized with ECLK signal)

In asynchronous mode, the chip select is asserted synchronized with AS or DS.

The DSACK field is not used in synchronous mode because a bus cycle is only performed as a syn-

chronous operation. When a match condition occurs on a chip select programmed for synchronous op-

eration, the chip select signals the EBI that an ECLK cycle is pending.

BYTE —Upper/Lower Byte Option

This field is used only when the chip-select 16-bit port option is selected in the pin assignment register.

The following table lists upper/lower byte options.

Block Size Field

Block Size

Address Lines Compared

000

2 K

ADDR[23:11]

001

8 K

ADDR[23:13]

010

16 K

ADDR[23:14]

011

64 K

ADDR[23:16]

100

128 K

ADDR[23:17]

101

256 K

ADDR[23:18]

110

512 K

ADDR[23:19]

111

1 M

ADDR[23:20]

CSORBT —Chip-Select Option Register Boot ROM

$YFFA4A

MODE

BYTE

R/W

STRB

DSACK

SPACE

IPL

AVEC

RESET:

CSOR[10:0] —Chip-Select Option Registers

$YFFA4E–$YFFA76

MODE

BYTE

R/W

STRB

DSACK

SPACE

IPL

AVEC

RESET:

Freescale Semiconductor, Inc.

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